US3689701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multisignaller associated with a time division multiplex switching center
Assignee: Alcatel Lucent NV
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Filing: 1970-03-31
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Granted: 1972-09-05
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Expires: 1990-03-31
Abstract
Abstract signalling Instructions connected to a PCM switching network in the same way as a number of trunks. The information it receives is in the form of program instructions supplied from a central processor. The signalling unit is so organized that it may process simultaneously 96 instructions controlling as many different operations in a selected exchange (supermultiplex of 192 channels). Three different types of instructions are provided. These instructions may be grouped into programs capable of controlling the functions of a telephone central exchange. The instructions are as follows: 1. INSTRUCTIONS WHICH CONTROL A DATA TRANSFER BETWEEN THE SIGNALLING UNIT AND ONE JUNCTOR, 2. Instructions which control the supervision of the line and establish the digit analysis and the digit transmission, and 3. Instructions which control the switching network path check.
Inventors
- 👤 Marc Edgar Marie Bosonnet
- 👤 Michel Andre Robert Henrion
- 👤 Jean-Pierre Lecorre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:35
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
224 words
A switching system comprising a first multisignaller for executing a plurality of instructions supplied by a switching computer employing a stored program, said first multisignaller employing wired logic, a PCM switching center, said first multisignaller and said switching computer assuming the functions of centralized control circuits for the PCM switching center, said first multisignaller comprising means for connecting the first multisignaller to a switching computer via a group of trunks with g/2 channels, memory means incorporating a memory of g/2 addresses operable in time division multiplex to store simultaneously the instructions concerning g/2 operations in the course of execution, means coupling said first multisignaller to the PCM switching center over g channels to enable connection of the first multisignaller either to a junctor, or to a trunk, or to a second multisignaller to carry out data transfers under the control of the stored instructions, means in the PCM switching center for comparing received data with transmitted data for determining the next operation, means for identifying each phase of an instruction by the value of a sequentially coded instruction, whereby, when all the operations are completed, the final value of the sequentially coded instruction indicates the result of the operation and alerts the first multisignaller and enables it to immediately call the computer if interrupt information is written in a particular position of the instruction.
Claim 2
Dependent Claim
224 words
A switching system comprising a first multisignaller for executing a plurality of instructions supplied by a switching computer employing a stored program, said first multisignaller employing wired logic, a PCM switching center, said first multisignaller and said switching computer assuming the functions of centralized control circuits for the PCM switching center, said first multisignaller comprising means for connecting the first multisignaller to a switching computer via a group of trunks with g/2 channels, memory means incorporating a memory of g/2 addresses operable in time division multiplex to store simultaneously the instructions concerning g/2 operations in the course of execution, means coupling said first multisignaller to the PCM switching center over g channels to enable connection of the first multisignaller either to a junctor, or to a trunk, or to a second multisignaller to carry out data transfers under the control of the stored instructions, means in the PCM switching center for comparing received data with transmitted data for determining the next operation, means for identifying each phase of an instruction by the value of a sequentially coded instruction, whereby, when all the operations are completed, the final value of the sequentially coded instruction indicates the result of the operation and alerts the first multisignaller and enables it to immediately call the computer if interrupt information is written in a particular position of the instruction.
Claim 3
Dependent Claim
129 words
A switching system according to claim 1 in which data transfer between the first multisignaller and a junctor involves five frames of information and concerns data collection in said junctor, together with data modification and a check of the modified data, means by which said transfers are carried out by writing, in a signaller, an instruction which controls the operation of a transfer unit, each of said instructions comprising a plurality of sub-instructions including a first for selection of the junctor and of the address concerned in the junctor which uses two frames, a second for data collection and data modification which uses a single frame, a third for a modified data check which uses a frame and a fourth for the end of operation which uses a frame.
Claim 4
Dependent Claim
187 words
A switching system as claimed in claim 2, in which the different frames are controlled in time succession by interpretation in an instruction processing circuit or by the instruction read in the first multisignaller, this instruction serving to control the setting up of a space path between the first multisignaller and the junctor by sending, at the readout time of the first multisignaller, marking signals over conductors which by-pass the switching network so that the connection is established without using the space division path memories, each junctor including means for elaborating signals identifying respective ones of said frames, where these signals provide control information either for the collection of data stored in the selected address then the storage, in said address, of a new code transmitted by the first multisignaller in the case of an instruction or the storage in said address of a new code and the transfer to the first multisignaller Of the code read in this address at the following frame in the case of an instruction, and that, in this last case, the instruction processing circuit controls the verification of the received code.
Claim 5
Dependent Claim
178 words
A switching system as claimed in claim 1 in which a first type of data transfer between the first multisignaller and a trunk concerns the supervision of signalling received over a channel of said trunk under the control of an instruction stored in the first multisignaller, that, for the said operations, a logical signalling circuit and a logical persistence circuit associated with the first multisignaller supply, at the end of selected periods, two informations characterizing respectively the value of the received signalling level and the fact that a level change has occurred in the channel, these informations being applied to instruction processing circuits provided for processing of selected instructions, a first instruction containing the measurement of the signalling level for a maximum duration of said selected periods and delivering an information of confirmed state of signalling if the level is the same during at least two of said selected periods and a further instruction controlling the test of the duration of a given signalling level during a predetermined interval the value of which is set by the computer.
Claim 6
Dependent Claim
37 words
A switching system as claimed in claim 1, in which additional data transfer between a first multisignaller and a trunk includes the transmission towards a switching center, of three digits, said transmission being controlled by an instruction.
Claim 7
Dependent Claim
101 words
A switching system according to claim 1, in which data transfer between said first and second multisignallers is through a space switching network and a time switching network in the PCM switching center for checking the space division and time division paths established between said two multisignallers, control of the space switching and time switching networks being established by an instruction stored in each of said multisignallers, said instruction being carried out by exchange of codes and comparison of the received code to the transmitted code in each multisignaller whereby the result of the comparison constitutes the result of the operation.
References Cited (Backward Citations)
US3401235A
Cited
US3492430A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-05 | 1976-03-06 | 1976-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-05 | 1980-03-06 | 1980-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-05 | 1984-03-06 | 1984-09-05 | $7700.00 | Window Closed / Lapsed |