Abstract In this invention a phase-locked-loop has a phase detector which is prevented from passing negative pulses from a first to second terminal, to lower the frequency of the clock signal, whenever synchronizing signal is lost. The synchronizing signal goes to a monostable flip-flop, that puts out a reset signal to a flipflop, that provides a positive gate enable signal. The negative pulses from the first terminal of the phase detector go through an inverter to one input of a NAND gate, the positive gate enable signal goes to the second input. The output of the gate goes to the second terminal of the phase detector. The flip-flop is continuously set (removing the gate enable signal) and reset (regaining the gate enable signal) so long as the synchronizing signal is present. When the synchronizing signal is lost, the flip-flop is not reset and the gate enable signal is lost until the synchronizing signal returns.
In an apparatus for controlling a phase-locked-loop to prevent lowering of the frequency of its output clock signal in response to loss of synchronizing signal, said phase-locked-loop including a phase detector, in which the means to cause a decrease in frequency provides a control signal at a first terminal to be transmitted to a second terminal, the improvement comprising: a. gate means to control the passage of said control signal from said first to said second terminal; b. first means responsive to a negative-going transition in said synchronizing signal to create a pulse; c. second means responsive to said pulse of said first means, for creating a gate-enable signal to said gate means; and d. third means responsive to said gate enable signal and said clock signal to disable said second means; whereby said gate means is prevented from being enabled and said control signal is prevented from passing to said second terminal.
Claim 2
Dependent Claim
153 words
In an apparatus for controlling a phase-locked-loop to prevent lowering of the frequency of its output clock signal in response to loss of synchronizing signal, said phase-locked-loop including a phase detector, in which the means to cause a decrease in frequency provides a control signal at a first terminal to be transmitted to a second terminal, the improvement comprising: a. gate means to control the passage of said control signal from said first to said second terminal; b. first means responsive to a negative-going transition in said synchronizing signal to create a pulse; c. second means responsive to said pulse of said first means, for creating a gate-enable signal to said gate means; and d. third means responsive to said gate enable signal and said clock signal to disable said second means; whereby said gate means is prevented from being enabled and said control signal is prevented from passing to said second terminal.
Claim 3
Dependent Claim
62 words
The apparatus as in claim 1 in which said gate means comprises a NAND gate, the output of which is connected to said second terminal, said first terminal connected through an inverter to the first input of said NAND gate, and the second input of said NAND gate receiving a positive gate enable signal, so long as said synchronizing signal is present.
Claim 4
Dependent Claim
36 words
The apparatus as in claim 2 in which said positive gate enable signal is provided by resetting a flip-flop, the resetting signal being received from a monostable flip-flop, whose input is connected to said synchronizing signal.
Claim 5
Independent Claim
41 words
The apparatus as in claims 3 including said third means comprising an AND gate, the output of which provides the set signal to said flip-flop, and the two inputs to which comprise said clock signal and said positive gate enable signal.