Organ stop memory circuit

Claim 2

An organ stop memory circuit for use witH an organ stop which is useable in a plurality of voice combinations, said memory circuit comprising: a plurality of magnetic memory cores, one for each of said combinations; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor; for each storage capacitor, switching means operable in response to the selection of a respective one of said voice combinations for discharging the respective capacitor through the respective first winding thereby to polarize the respective core in a first sense; and means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during selection of one of said voice combinations, for setting said stop and for recharging any discharged storage capacitor through the respective first winding for restoring the polarization of the respective core to said opposite magnetic sense.

Claim 3

An organ stop memory circuit for use with an organ stop which is useable in a plurality of voice combinations, said memory circuit comprising: a plurality of magnetic memory cores, one for each of said combinations; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor; for each storage capacitor, first switching means operable in response to the application of a respective input signal indicating the selection of a respective one of said voice combinations for discharging the respective capacitor through the respective first winding thereby to polarize the respective core in a first sense; means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during selection of one of said voice combinations, for generating an output signal; drive means responsive to said output signal for setting said stop; second switching means, responsive to said output signal, for abruptly recharging any discharged storage capacitor through the respective first winding for restoring the polarization of the respective core to said opposite magnetic sense; and means for recharging any discharged storage capacitor which is not recharged by said second switching means, relatively slowly and without changing the magnetic polarization of the respective core.

Claim 4

An organ stop memory circuit for use with an organ stop which is useable in a plurality of voice combinations, said memory circuit comprising: a plurality of magnetic memory cores, one for each of said combinations; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor; for each storage capacitor, first switching means operable in response to the application of a respective input signal indicating the selection of a respective one of said voice combinations for discharging the respective capacitor through the respective first winding thereby to polarize the respective core in a first sense; means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during selection of one of said voice combinations, for generating an output signal; drive means responsive to said output signal for setting said stop; second switching means, responsive to said output signal, for abruptly recharging any discharged storage capacitor through the respective first winding for restoring the polarization of the respective core to said opposite magnetic sense; and means for recharging any discharged storage capacitor which is not recharged by said second switching means, relatively slowly and without changing the magnetic polarization of the respective core.

Claim 5

A memory circuit as set forth in claim 2 further comprising means responsive to the application of input signals corresponding to the selection of more than one combination for inhibiting operation of said first switching means.

Claim 6

A magnetic core memory circuit for holding a predetermined plurality of binary information bits, said memory circuit comprising: a plurality of magnetic memory cores, one for each bit of binary information to be held; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor; a plurality of input terminals for receiving input signals defining which of said plurality of bits of information is to be read out; for each storage capacitor, first switching means operable in response to a respective input signal for abruptly discharging the respective capacitor through the respective first winding thereby to polarize the respective core in a first sense; means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during discharge of the respective storage capacitor, for providing an output signal indicating the previously existing state of the respective core; second switching means, responsive to an oUtput signal indicating that the polarization of the selected core was previously in said opposite sense, for abruptly recharging any discharged storage capacitor through the respective first winding for restoring the polarization of the selected core to said opposite magnetic sense; and means for recharging any discharged storage capacitor which is not recharged by said second switching means, relatively slowly and without changing the magnetic polarization of the respective magnetic core.

Claim 7

A magnetic core memory circuit for holding a predetermined plurality of binary information bits, said memory circuit comprising: a plurality of magnetic memory cores, one for each bit of binary information to be held; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor; a plurality of input terminals for receiving input signals defining which of said plurality of bits of information is to be read out; for each storage capacitor, first switching means operable in response to a respective input signal for abruptly discharging the respective capacitor through the respective first winding thereby to polarize the respective core in a first sense; means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during discharge of the respective storage capacitor, for providing an output signal indicating the previously existing state of the respective core; second switching means, responsive to an oUtput signal indicating that the polarization of the selected core was previously in said opposite sense, for abruptly recharging any discharged storage capacitor through the respective first winding for restoring the polarization of the selected core to said opposite magnetic sense; and means for recharging any discharged storage capacitor which is not recharged by said second switching means, relatively slowly and without changing the magnetic polarization of the respective magnetic core.

Claim 8

A magnetic core memory circuit for holding a predetermined plurality of binary information bits, said memory circuit comprising: a plurality of magnetic memory cores, one for each bit of binary information to be held; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor which is interconnected with one end of the respective first winding; a plurality of input terminals for receiving input signals defining which of said plurality of bits of information is to be read out; for each storage capacitor, a discharge transistor, the collector terminal of which is interconnected with the respective capacitor, the respective input terminal being interconnected with the base terminal of each transistor for biasing that transistor toward conduction when the respective bit is to be read out; a charging transistor, interconnected with said capacitors through respective diodes, for charging any discharged capacitor when a reset signal is applied to said charging transistor; a readout transistor, the emitter terminals of said discharge transistors being connected in common through said readout transistor to the other end of said first windings thereby to cause a forward-biased discharge transistor to discharge the respective storage capacitor when the readout transistor conducts; and means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during discharge of the respective storage capacitor, for applying a reset signal to said charging transistor thereby to restore the polarization of the selected core to said opposite magnetic sense; and means for selectively forward biasing said readout transistor after an input signal is applied to one of said input terminals.

Claim 9

A magnetic core memory circuit for holding a predetermined plurality of binary information bits, said memory circuit comprising: a plurality of magnetic memory cores, one for each bit of binary information to be held; for each core, a first winding linking the core and adapted to magnetically polarize the core in either sense; for each of said first windings, a charge storage capacitor which is interconnected with one end of the respective first winding; a plurality of input terminals for receiving input signals defining which of said plurality of bits of information is to be read out; for each storage capacitor, a discharge transistor, the collector terminal of which is interconnected with the respective capacitor, the respective input terminal being interconnected with the base terminal of each transistor for biasing that transistor toward conduction when the respective bit is to be read out; a charging transistor, interconnected with said capacitors through respective diodes, for charging any discharged capacitor when a reset signal is applied to said charging transistor; a readout transistor, the emitter terminals of said discharge transistors being connected in common through said readout transistor to the other end of said first windings thereby to cause a forward-biased discharge transistor to discharge the respective storage capacitor when the readout transistor conducts; and means, including a second winding on each of said cores, responsive to a change in the magnetic polarization of any one of said cores to said first sense from the opposite magnetic sense, during discharge of the respective storage capacitor, for applying a reset signal to said charging transistor thereby to restore the polarization of the selected core to said opposite magnetic sense; and means for selectively forward biasing said readout transistor after an input signal is applied to one of said input terminals.

Claim 10

A memory circuit as set forth in claim 5 further comprising means for inhibiting conduction through said readout transistor if more than one of said discharge transistors is forward biased.