US3686469A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Steady state phase error correction circuit
Assignee: Ampex Corp
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Filing: 1970-04-02
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Granted: 1972-08-22
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Expires: 1990-04-02
Abstract
Abstract In a servo system in which the angular phase of a rotating member is synchronized to the phase of a reference signal by a dynamic servo loop, circuitry is shown operating in cooperation with the dynamic servo loop for developing a variable DC bias signal for eliminating residual phase errors remaining during the dynamic servo control. In particular, the rotating member is embodied by a rotary transducer assembly carried by a wideband magnetic tape transport in which the transducer assembly is to be rotatably controlled by the servo systems so as to scan a prerecorded signal carried by the magnetic tape at a rate and phase which causes the signal thereby reproduced to occur in synchronous with a reference timing signal. The variable DC phase bias signal is developed by increasing or decreasing the level of an up/down binary counter by feeding relatively low rate clock pulses thereto and conditioning the direction of the counter in accordance with the detection of phase lead or phase lag between the reference and reproduce signals. A digital-to-analog converter is coupled to and responsive to the counting level of the binary counter to issue a step variable DC voltage having a magnitude and polarity corresponding to the number of counting states and the direction thereof away from a normal mid-modulus count level of the counter preselected as the nominal or zero phase error operating point of the circuit.
Inventors
- 👤 Harold V Clark
- 👤 Gerald C Engbretson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:53
CPC Classifications
G; G11; G11B; G11B15/00; G11B15/18; G11B15/1808
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
162 words
A circuit for developing a variable DC error signal for eliminating static phase errors in a dynamically phase controlled servo system, comprising: clock pulses generator means, phase lead and lag detector means for sensing the direction in which such static phase error occurs, counting means connected to said clock pulse generator for registering a change in count in response to said clock pulses and having a count direction control connected to said detection means, said detection means disposing said direction control so that said counter means changes count in one direction in response to a detected lead phase error and changes count in the other direction in response to a detected lag phase error, and digital-to-analog cOnverter means connected to said counter and having an output developing an incrementally variable DC signal in response to the count registered by said counter, whereby said output signal serves as a phase error bias signal for correcting steady state phase errors in the servo system.
Claim 2
Dependent Claim
162 words
A circuit for developing a variable DC error signal for eliminating static phase errors in a dynamically phase controlled servo system, comprising: clock pulses generator means, phase lead and lag detector means for sensing the direction in which such static phase error occurs, counting means connected to said clock pulse generator for registering a change in count in response to said clock pulses and having a count direction control connected to said detection means, said detection means disposing said direction control so that said counter means changes count in one direction in response to a detected lead phase error and changes count in the other direction in response to a detected lag phase error, and digital-to-analog cOnverter means connected to said counter and having an output developing an incrementally variable DC signal in response to the count registered by said counter, whereby said output signal serves as a phase error bias signal for correcting steady state phase errors in the servo system.
Claim 3
Dependent Claim
75 words
In a transport system as defined by claim 1, the combination wherein said counter means and digital to analog converter means are cooperatively adjusted to provide a zero static error signal at substantially mid-count of the counting range provided by said counter, and further comprising circuit means responsive to the maximum and minimum counting states of said counter means and the direction control thereof for inhibiting response of said counter means to said clock pulses.
Claim 4
Dependent Claim
194 words
In a transport system having a rotary transducer assembly for scanning prerecorded tracks on a record medium as such medium is advanced passed the assembly and a servo means for controlling the phase of rotation of the transducer assembly such that a reproduced synchronizing signal from the medium is dynamically phase locked to a reference synchronizing signal, the combination comprising: counter means for receiving a train of clock pulses, said counter means having a count direction control selectively conditioning said counter means to count up or down in response to said clock pulses; phase lead and lag detector means connected to said counter direction control and for receiving the reproduced synchronizing signal and the reference synchronizing signal for disposing said counter direction control in one direction in response to the detection of a lead phase relationship between said synchronizing pulses and disposing said counter control in the other direction in response to a lag phase relationship between said synchronizing pulses; and digital to analog converter means connected to said counter means developing a static analog error signal for connection to said servo means for static phase control of the rotational phase of transducer assembly.
Claim 5
Dependent Claim
194 words
In a transport system having a rotary transducer assembly for scanning prerecorded tracks on a record medium as such medium is advanced passed the assembly and a servo means for controlling the phase of rotation of the transducer assembly such that a reproduced synchronizing signal from the medium is dynamically phase locked to a reference synchronizing signal, the combination comprising: counter means for receiving a train of clock pulses, said counter means having a count direction control selectively conditioning said counter means to count up or down in response to said clock pulses; phase lead and lag detector means connected to said counter direction control and for receiving the reproduced synchronizing signal and the reference synchronizing signal for disposing said counter direction control in one direction in response to the detection of a lead phase relationship between said synchronizing pulses and disposing said counter control in the other direction in response to a lag phase relationship between said synchronizing pulses; and digital to analog converter means connected to said counter means developing a static analog error signal for connection to said servo means for static phase control of the rotational phase of transducer assembly.
Claim 6
Dependent Claim
49 words
In the transport system of claim 3, the combination further comprising: pulse coincidence detection means for receiving the reproduce and reference synchronizing pulses and being connected to said counter means for inhibiting change of count thereof in response to detection of coincidence between the reproduced and reference synchronizing pulses.
Claim 7
Dependent Claim
57 words
In a transport system as defined by claim 3, the combination further comprising: pulse frequency divider means having an input for receiving the pulses from one of said synchronizing signals and having an output connected to said counter for providing said clock pulses at a frequency less than the frequency of said reproduce and reference synchronizing signals.
Claim 8
Dependent Claim
139 words
Method of developing a variable direct current error signal for eliminating static phase errors in a dynamically phase controlled servo system, the steps comprising: developing a train of clock pulses, detecting static lead and lag phase errors of the system, counting said train of clock pulses in a counter to register a pulse counting state therein, applying said pulse train to change the count on said counter in a first direction in response to a detected phase lead error and applying said train of clock pulses to change the count on said counter in the other direction in response to a detected phase lag error of said system, and developing an analog error signal having a magnitude responsive to the counting state of said counter and being fed to and for effecting static phase corrections in the servo system.
Claim 9
Dependent Claim
139 words
Method of developing a variable direct current error signal for eliminating static phase errors in a dynamically phase controlled servo system, the steps comprising: developing a train of clock pulses, detecting static lead and lag phase errors of the system, counting said train of clock pulses in a counter to register a pulse counting state therein, applying said pulse train to change the count on said counter in a first direction in response to a detected phase lead error and applying said train of clock pulses to change the count on said counter in the other direction in response to a detected phase lag error of said system, and developing an analog error signal having a magnitude responsive to the counting state of said counter and being fed to and for effecting static phase corrections in the servo system.
Claim 10
Dependent Claim
90 words
The method as defined in claim 6, wherein the servo system is arranged to synchronize a reproduced information signal from a magnetic tape transport with a reference signal, the steps further defined by the timing relationship between the reproduced information signal and the reference signal being used to detect phase lead and lag of the servo system, and the step of developiNg said train of clock pulses being provided by frequency divider means responsive to the reference signal for producing clock pulses at a rate less than the frequency thereof.
Claim 11
Dependent Claim
29 words
The method of claim 6, further comprising the step of inhibiting change of said counter in response to the servo system assuming a condition of zero static phase error.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-22 | 1976-02-21 | 1976-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-22 | 1980-02-21 | 1980-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-22 | 1984-02-21 | 1984-08-22 | $7700.00 | Window Closed / Lapsed |