Non-linear quantization of reference amplitude level time crossing intervals

Claim 3

The method of claim 1 wherein said predetermined amplitudes have a constant value.

Claim 4

The method of claim 1 wherein said predetermined amplitudes vary in dependence on either or both the amplitude and frequency of said electrical input signal.

Claim 5

The method of claim 1 further comprising the step of: preferentially amplifying the components of the frequency spectrum of said input signal which characteristically have a low amplitude to ensure that said components achieve said predetermined amplitudes.

Claim 6

The method of claim 1 further including: the step of frequency inversion of said electrical input signal prior to the step of determining said time intervals between successive occurrences of predetermined amplitudes.

Claim 7

The method of claim 1, wherein said quantization is effected by passing said first electrical output signal to one input of a coincidence circuit the other input of which is fed by a signal of predetermined substantially constant frequency.

Claim 8

The method of claim 6, wherein said predetermined substantially constant frequency is at least twice the highest frequency of the electrical input signal.

Claim 9

The method of claim 1, wherein said non-linear quantization is effected in such a way as to produce a substantially equal number of different pulse lengths to represent each octave within the frequency range of the original signal waveform.

Claim 10

A circuit for encoding an electrical input signal representing a waveform such as a speech waveform, comprising: means for determining the time intervals between successive occurrences of predetermined amplitudes and for providing a first electrical output signal having pulses of different lengths each indicative of the length of respective said time intervals; means for quantizing said pulse lengths of said first electrical output signal to produce a digital electrical output signal; and means for prOviding quantized pulses of a predetermined length from selected quantized pulse lengths of said digital electrical output signal to effect a non-linear quantization of said first electrical output signal.

Claim 11

A circuit for encoding an electrical input signal representing a waveform such as a speech waveform, comprising: means for determining the time intervals between successive occurrences of predetermined amplitudes and for providing a first electrical output signal having pulses of different lengths each indicative of the length of respective said time intervals; means for quantizing said pulse lengths of said first electrical output signal to produce a digital electrical output signal; and means for prOviding quantized pulses of a predetermined length from selected quantized pulse lengths of said digital electrical output signal to effect a non-linear quantization of said first electrical output signal.

Claim 12

The circuit of claim 9 wherein there are provided means for selectively amplifying components of the frequency spectrum of the input signal which characteristically have a low amplitude to ensure that these components achieve said predetermined amplitudes.

Claim 13

The circuit of claim 9, wherein said means for providing said first electrical output signal having pulses of different lengths comprises an infinite clipping circuit.

Claim 14

The circuit of claim 9, wherein said means for providing predetermined quantized pulse lengths from selected quantized pulse lengths to effect a non-linear quantization of said first electrical output signal comprise: a first shift register having a serial input, and a plurality of parallel outputs, one for each stage of said register and a second shift register having a serial input, a serial output, and a plurality of parallel inputs, one for each stage of said register, the parallel outputs of said first shift register being interconnected with the parallel inputs of said second shift register such that the stages of said first shift register positioned to receive a selected pulse length are coupled to the stages of said second shift rwgister positioned to hold said predetermined pulse lengths which are to be provided in place of said selected pulse lengths.

Claim 15

The circuit of claim 12, wherein said digital electrical output signal has only two discrete amplitudes and said first shift register is a dual register each side of which handles signals representing a respective amplitude of said electrical output signal.

Claim 16

The circuit of claim 13, wherein said dual register also has a plurality of parallel outputs, one for each stage of said dual register; a third shift register having a serial input, a serial output, and a plurality of parallel inputs, one for each stage of said register; said parallel outputs of said dual register being interconnected with said parallel inputs of said third shift register such that the stages of said dual register positioned to receive selected pulse lengths are coupled to stages of said third shift register positioned to hold said predetermined pulse lengths which are to be provided in place of said selected pulse lengths.

Claim 17

The circuit of claim 14, wherein said second and said third shift registers also have a plurality of parallel outputs, one from each stage of said register, said parallel outputs being fed to a preset input of each corresponding stage in said first and said dual register to ensure that corresponding stages are always in the same state when said second and third registers are in use.

Claim 18

A circuit for decoding a quantized digital signal of the type encoded in dependence on the time intervals between successive occurrences of predetermined amplitudes in the original information signal comprising: a. a variable output circuit, b. means for determining the length of each successive pulse of said digital signal, c. means for delaying said digital signal, d. means for adjusting said variable output circuit in dependence on said pulse length while said delay means is delaying said pulse length of said signal, and e. means for passing said digital signal to said adjusted output circuit to provide an output waveform related to said quantized digital signal.

Claim 19

A circuit for decoding a quantized digital signal of the type encoded in dependence on the time intervals between successive occurrences of predetermined amplitudes in the original information signal comprising: a. a variable output circuit, b. means for determining the length of each successive pulse of said digital signal, c. means for delaying said digital signal, d. means for adjusting said variable output circuit in dependence on said pulse length while said delay means is delaying said pulse length of said signal, and e. means for passing said digital signal to said adjusted output circuit to provide an output waveform related to said quantized digital signal.

Claim 20

The circuit of claim 16, wherein said variable output circuit is a low pass filter circuit the frequency response of which is adjustable such that the cutoff frequency is decreased to a relatively low value for a long pulse, and increased to a relatively high value for a short pulse.

Claim 21

The circuit of claim 17, wherein said means for determining the length of successive pulses comprises: a dual shift register having a plurality of parallel outputs, one for each stage of said register; second aNd third shift registers having a plurality of parallel inputs, one for each stage of each said register; said parallel outputs of said dual register being interconnected with said parallel inputs of said second and third shift registers whereby a train of like pulses which is about to pass out of said dual register will switch a corresponding number of stages of said second or said third register to provide an indication of the pulse length of the signal about to pass to said variable filter circuit.

Claim 22

The circuit of claim 18, wherein said means for determining the length of successive pulses further includes: said second and third shift registers having a plurality of parallel outputs, one for each stage of said registers; two analogue adding circuits, the inputs of respective said analogue adding circuits being coupled to respective said parallel outputs of said second and third shift registers; the outputs of said analogue adding circuits being coupled to a control input of said variable filter circuit.

Claim 23

The circuit of claim 17, wherein said variable filter circuit comprises a plurality of fixed filter circuits each having a different frequency response, and a cooperating switching circuit for selecting the appropriate filter in dependence on the length of the pulse to be decoded.

Claim 24

The circuit of claim 20, wherein said means for determining the length of successive pulse comprises: a dual shift register having a serial input, a serial output to the variable filter circuit, and a plurality of parallel outputs, one for each stage of the register; second and third shift registers each having a plurality of parallel inputs and a plurality of parallel outputs, one of each for each stage of each of said registers; means interconnecting said parallel outputs of respective sides of said dual register with said parallel inputs of said second and third registers respectively, whereby a train of like pulses which is about to pass out of said dual register will switch a corresponding number of stages of whichever of said second or third registers is connected to that side of said dual register; and a plurality of exclusive OR gates coupled to said parallel outputs of said second and third registers whereby the end of said train of like pulses is detected and a signal passed to the appropriate part of said switching circuit.