US3681760A
Expired / Lapsed
US
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Binary signal utilization and selective address detection system
Assignee: Motorola Solutions Inc
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Filing: 1970-08-24
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Granted: 1972-08-01
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Expires: 1990-08-24
Abstract
Abstract A binary signal utilization and selective address detection system for an electronic printer wherein a first storage register serially accepts and stores binary signals in a binary signal train, then simultaneously couples all binary signals in the first storage register to a transfer register. The transfer register is provided to allow binary address signals entered into both registers to be sampled by a detector for a desired binary address. If the desired binary address is recognized, the detector causes subsequent binary print signals to cause operation of electronic printer hammers. Such print signals are serially applied to the first storage register, and then simultaneously transferred to the transfer register which applies them to electronic printer hammers while the succeeding binary signals in the binary signal train are serially entered into the first storage register.
Inventors
- 👤 Roger F Salava
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:48
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/22; G06K; G06K15/00; G06K15/02; G06K15/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
177 words
A binary signal utilization and selective address detection system for a train of binary signals wherein said system includes in combination; input means for receiving said train of binary signals; first storage means coupled to said input means for serially receiving and storing said binary signals, second storage means coupled to said first storage means, said second storage means being operative to simultaneously receive all said binary signals from said first storage means and store said binary signals therein, utilization means coupled to said second storage means, said utilization means being operative to simultaneously utilize all said binary signals in said second storage means, binary signal detection means coupled to said first and second storage means, said binary signal detection means being operative to develop a detection signal in response to particular combinations of binary signals in both said first and second storage means, and control means coupled to said detection means and utilization means and responsive to said detection signal to control the application of binary signals from said second storage means to said utilization means.
Claim 2
Dependent Claim
177 words
A binary signal utilization and selective address detection system for a train of binary signals wherein said system includes in combination; input means for receiving said train of binary signals; first storage means coupled to said input means for serially receiving and storing said binary signals, second storage means coupled to said first storage means, said second storage means being operative to simultaneously receive all said binary signals from said first storage means and store said binary signals therein, utilization means coupled to said second storage means, said utilization means being operative to simultaneously utilize all said binary signals in said second storage means, binary signal detection means coupled to said first and second storage means, said binary signal detection means being operative to develop a detection signal in response to particular combinations of binary signals in both said first and second storage means, and control means coupled to said detection means and utilization means and responsive to said detection signal to control the application of binary signals from said second storage means to said utilization means.
Claim 3
Dependent Claim
113 words
The binary signal utilization and selective address detection system of claim 1 wherein said control means has portions coupled to said input means, said second storage means, said utilization means, and said binary signal detection means, said control means being operative in response to the receipt of a first predetermined number of binary signals to enable said second storage means, said control means being operative in response to the receipt of a second predetermined number of binary signals to enable said binary signal detection means, said control means being further operative in response to the receipt of said first predetermined number of binary signals and said detection signal to enable said utilization means.
Claim 4
Dependent Claim
26 words
The binary signal utilization and selective address detection system of claim 2 wherein said first storage means includes a storage register having a plurality of stages.
Claim 5
Dependent Claim
19 words
The binary signal utilization and selective address detection system of claim 3 wherein said storage register includes six stages.
Claim 6
Dependent Claim
32 words
The binary signal utilization and selective address detection system of claim 3 wherein said second storage means includes a storage register having the same number of stages as said first storage means.
Claim 7
Dependent Claim
98 words
The binary signal utilization and selective address detection system of claim 5 wherein said utilization means includes a printer having printer hammer means and printer hammer driver means coupled to said second storage means and said control means, said printer hammer driver means being enabled by said control means to develop printer hammer driving signals in response to said binary signals in said second storage means, said printer hammer means being coupled to said printer hammer driver means for printing dot formed characters, said printer hammer means operative in response to said driving signals to print said dots.
Claim 8
Dependent Claim
166 words
The binary signal utilization and selective address detection system of claim 5 wherein said control means includes, clock means coupled to said input circuit means, said clock means developing timing pulses in accordance with said binary signals in said train of binary signals, and counter means coupled to said clock means, said second storage means, said utilization means, and said binary signal detection means, said counter means being operative in response to said timing pulses to cyclically count to a first particular number equal to said predetermined number of binary signals and develop a first counting signal for enabling said second storage means, said counter means being further operative in response to said first counting signals to count to a sEcond particular number equal to said second predetermined number of binary signals and develop a second counting signal for enabling said binary signal detection means, said counter means being further operative to couple said first counting signals to said utilization means to enable said utilization means.
Claim 9
Dependent Claim
27 words
The binary signal utilization and selective address detection system of claim 7 wherein said counter means includes means operative to count to said second particular number twice.
Claim 10
Dependent Claim
113 words
The binary signal utilization and selective address detection system of claim 7 wherein said binary signal detection means includes, a plurality of inverter means each having an input coupled to said first and second storage means, and having first and second outputs, said inverter means being responsive to said binary signals coupled thereto from said first and second storage means to develop an inverted signal at said first output and a non-inverted signal at said second output, and AND gate means selectively coupled to particular ones of said first and second inverter outputs, said AND gate means responsive to particular combinations of inverted and non-inverted signals coupled thereto to develop said detection signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-01 | 1976-01-31 | 1976-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-01 | 1980-01-31 | 1980-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-01 | 1984-01-31 | 1984-08-01 | $7700.00 | Window Closed / Lapsed |