High speed pim demodulator

Claim 2

Apparatus for providing in a first operating mode a blanking signal output in response to an input signal having an amplitude below a predetermined threshold and for providing in a second operating mode a demodulated output in response to a PIM input signal having an amplitude above a predetermined threshold comprising: first capacitor means, second capacitor means, means for alternately charging said first and second capacitor means to substantially the same predetermined voltage, means for alternately discharging said first and second capacitor means at a substantially constant discharge rate, means receiving said input signal for controlling said discharging means to generate a series of ramp waveforms alternately at said first and second capacitor means, said first and second capacitor means alternately charging and discharging, said ramp waveforms having substantially equal time periods in said first operating mode, and for controlling said discharging means to generate a series of ramp waveforms having time periods proportional in length to the semi-period lengths of the PIM input signal in said second operating mode, means responsive to said input signals for placing said controlling means in said first operating mode when said input signal has an amplitude below a predetermined threshold level and for placing said controlling means in said second operating mode when said PIM modulated input signal has an amplitude above a predetermined level, means connected to said first and second capacitor means for providing a composite sawtooth waveform composed of alternatingly generated ramps, and means for averaging said composite sawtooth waveform to provide a demodulated output signal.

Claim 3

Apparatus according to claim 1 wherein said charging means comprising: a voltage source, first and second diode means, first and second resistor means means for alternately connecting in series a first branch comprising said voltage source, said first resistor means, said first capacitor means, and said first diode means, one end of said first diode means being connected to ground, and a second branch comprising said voltage source, said second resistor means, said second capacitor means, and said second diode means, one end of said second diode means being connected to ground whereby said first and second capacitor means are alternately charged in a series RC circuit between said voltage source and ground.

Claim 4

Apparatus according to claim 2 wherein said means for alternately connecting in series said first and second branches comprises first and second transistors having their emitters connected between said first resistor means and said first capacitor means and between said second resistor means and said second capacitor means, respectively, and having their collectors connected to ground.

Claim 5

Apparatus according to claim 3 wherein said means for alternately discharging said first and second capacitor means comprises current source means.

Claim 6

Apparatus according to claim 4 wherein said means for controlling said discharging means comprises: third and fourth transistors having their bases connected respectively to said first and second capacitor means and having their emitters connected to said constant current source means, fifth and sixth transistors receiving said input signal at the bases thereof and having their collectors connected to the emitters of said third and fourth transistors, first and second diodes having their cathodes connected to the collectors of said fifth and sixth transistors and having their anodes connected together, and a seventh transistor having its collector connected to the junction of said diode anodes and having its emitter connected to said constant current source means.

Claim 7

Apparatus according to claim 5 wherein said means for placing said controlling means in said first and second oPerating modes comprises biasing means connected to the bases of said fifth, sixth, and seventh transistors for providing alternate conduction of said fifth and sixth transistors in response to an input signal above a threshold set by said biasing means and conduction of said fifth transistor when said input signal is below the threshold set by said biasing means.

Claim 8

Apparatus according to claim 6 wherein said means for providing a composite waveform comprises a pair of closely matched transistors in a common emitter amplifier configuration connected to said first and second capacitor means, respectively.

Claim 9

Apparatus according to claim 7 wherein said means for providing a composite waveform comprises first and second diodes connected to said first and second capacitor means, respectively.

Claim 10

Apparatus according to claim 4 wherein said means for controlling said discharging means comprises third and fourth transistors having their bases connected respectively to said first and second capacitor means and having their emitters connected to said constant current means, and fifth and sixth transistors receiving said input signal at the bases thereof and having their emitters connected to the emitters of said third and fourth transistors in a differential pair configuration.

Claim 11

Apparatus according to claim 9 wherein said means for placing said controlling means in said first and second operating modes comprises biasing means connected to the bases of said third and fourth transistors for providing alternate conduction of said third and fourth transistors in a self-oscillating mode when said input signal level is below the threshold set by said biasing means and for providing alternate conduction of said third and fourth transistors as determined by the conduction of said fifth and sixth transistors when said input signal level exceeds said threshold.

Claim 12

Apparatus according to claim 10 wherein said means for providing a composite waveform comprises a pair of closely matched transistors in a common emitter amplifier configuration connected to said first and second capacitor means, respectively.

Claim 13

Apparatus according to claim 10 wherein said means for providing a composite waveform comprises first and second diodes connected to said first and second capacitor means, respectively.

Claim 14

A pulse-interval modulation demodulator comprising: a pair of input terminals, first and second transistors, means for connecting said input terminals to the bases of each of said transistors, respectively, third and fourth transistors, means for connecting the emitters of said third and fourth transistors to the collectors of said first and second transistors, respectively, a first terminal connectable to a first voltage source means for connecting the collectors of said third and fourth transistors to said terminal connectable to a voltage source, fifth and sixth transistors, means for connecting the bases of said fifth and sixth transistors to the collectors of said third and fourth transistors, first and second capacitors, means for connecting the emitters of said fifth transistor, said first capacitor and the base of said third transistor in series, means for connecting the emitters of said sixth transistor, said second capacitor and the base of said fourth transistor in series, first and second diodes, means for connecting the anode of said first diode to the base of said third transistor, means for connecting the cathode of said first diode to ground, means for connecting the anode of said second diode to the base of said fourth transistor, means for connecting the cathode of said anode to ground, first, second, third, and fourth resistors, a second terminal connectable to a second voltage source, means for connecting said first resistor between the cathode of said first diode and said second terminal, means for connecting said second resistor between the emitter of saId fifth transistor and said second terminal, means for connecting said third resistor between the emitter of said sixth transistor and said second terminal, means for connecting said fourth resistor between the anode of said second diode and said second terminal, third and fourth diodes, means for connecting the cathodes of said diodes to the emitters of said third and fourth transistors, respectively, seventh and eighth transistors, means for connecting the cathodes of said third and fourth diodes to the collector of said seventh transistor, means for connecting the emitters of said first, second, and seventh transistors to the collector of said eighth transistor, means for biasing said first and second transistors off in the absence of an input signal above a threshold level at said input terminals, means for biasing said seventh transistor on in the absence of an input signal above a threshold level at said input terminals, a third terminal connectable to a third voltage source, a variable resistor, means for connecting the emitter of said eighth transistor in series with said variable resistor to said third terminal, means for biasing said eighth transistor on whereby a constant current is provided at its collector being variable by said variable resistor, ninth and 10th transistors, means for connecting the bases of said third and fourth transistors to the bases of said ninth and 10th transistors, respectively, means for connecting the emitters of said ninth and 10th transistors to said second terminal, a low pass filter having first and second ends, an output terminal, means for connecting the first end of said low pass filter to the collectors of said ninth and 10th transistors, means for connecting the second end of said low pass filter to said output terminal, and means for connecting the second end of said low pass filter to said third terminal.

Claim 15

A pulse-interval modulation demodulator comprising: a pair of input terminals, first and second transistors, means for connecting said input terminals to the bases of each of said transistors, respectively, third and fourth transistors, means for connecting the emitters of said third and fourth transistors to the collectors of said first and second transistors, respectively, a first terminal connectable to a first voltage source means for connecting the collectors of said third and fourth transistors to said terminal connectable to a voltage source, fifth and sixth transistors, means for connecting the bases of said fifth and sixth transistors to the collectors of said third and fourth transistors, first and second capacitors, means for connecting the emitters of said fifth transistor, said first capacitor and the base of said third transistor in series, means for connecting the emitters of said sixth transistor, said second capacitor and the base of said fourth transistor in series, first and second diodes, means for connecting the anode of said first diode to the base of said third transistor, means for connecting the cathode of said first diode to ground, means for connecting the anode of said second diode to the base of said fourth transistor, means for connecting the cathode of said anode to ground, first, second, third, and fourth resistors, a second terminal connectable to a second voltage source, means for connecting said first resistor between the cathode of said first diode and said second terminal, means for connecting said second resistor between the emitter of saId fifth transistor and said second terminal, means for connecting said third resistor between the emitter of said sixth transistor and said second terminal, means for connecting said fourth resistor between the anode of said second diode and said second terminal, third and fourth diodes, means for connecting the cathodes of said diodes to the emitters of said third and fourth transistors, respectively, seventh and eighth transistors, means for connecting the cathodes of said third and fourth diodes to the collector of said seventh transistor, means for connecting the emitters of said first, second, and seventh transistors to the collector of said eighth transistor, means for biasing said first and second transistors off in the absence of an input signal above a threshold level at said input terminals, means for biasing said seventh transistor on in the absence of an input signal above a threshold level at said input terminals, a third terminal connectable to a third voltage source, a variable resistor, means for connecting the emitter of said eighth transistor in series with said variable resistor to said third terminal, means for biasing said eighth transistor on whereby a constant current is provided at its collector being variable by said variable resistor, ninth and 10th transistors, means for connecting the bases of said third and fourth transistors to the bases of said ninth and 10th transistors, respectively, means for connecting the emitters of said ninth and 10th transistors to said second terminal, a low pass filter having first and second ends, an output terminal, means for connecting the first end of said low pass filter to the collectors of said ninth and 10th transistors, means for connecting the second end of said low pass filter to said output terminal, and means for connecting the second end of said low pass filter to said third terminal.

Claim 16

A pulse-interval-modulation demodulator comprising: a pair of input terminals, first and second transistors, means for connecting said input terminals to the bases of each of said transistors, respectively, third and fourth transistors, fifth and sixth transistors, means for connecting the collectors of said third and fourth transistors to the bases of said fifth and sixth transistors, respectively, a first terminal connectable to a first voltage source, a variable resistor having first and second connections, means for connecting the first connection of said variable resistor to said first terminal and the second connection of said variable resistor to the emitter of said first and third transistors, means for connecting second end of said variable resistor to the emitters of said second and fourth transistors, first and second diodes, means for connecting the anodes of said diodes to the emitters of said first and third transistors and to the emitters of said second and fourth transistors, respectively, means for connecting the cathodes of said diodes to ground, a second terminal connectable to a second voltage source, means for connecting the collectors of said first and second transistors to said second terminal, means for connecting the bases of said fifth and sixth transistors to said second terminal, first, second, third, and fourth resistors, a third terminal connectable to a third voltage source, means for connecting said first resistor between the emitter of said fifth transistor and said third terminal, means for connecting said second resistor between the base of said third transistor and said second terminal, means for connecting said third resistor between the base of said fourth transistor and said second terminal, means for connecting said fourth resistor between the emitter of said sixth transistor and said third terminal, first and second capacitoRs, means for connecting said first capacitor between the emitter of said fifth transistor and the base of said fourth transistor, means for connecting said second capacitor between the emitter of said sixth transistor and the base of said third transistor, a diode ring comprising a first, second, third, and fourth diode in series to form four junctions, the cathodes of said first and second diodes being connected at a first junction, the anodes of said third and fourth diodes being connected at a second junction, the cathode of said third diode and the anode of said first diode being connected at a third junction, the cathode of said fourth diode and the anode of said second diode being connected at a fourth junction, means for connecting said first junction to ground, means for connecting said third junction to the base of said third transistor, means for connecting said fourth junction to the base of said fourth transistor, means for connecting said second junction to said second terminal, an output terminal, and means for connecting said second junction to said output terminal.

Claim 17

A pulse-interval-modulation demodulator comprising: a pair of input terminals, first and second transistors, means for connecting said input terminals to the bases of each of said transistors, respectively, third and fourth transistors, fifth and sixth transistors, means for connecting the collectors of said third and fourth transistors to the bases of said fifth and sixth transistors, respectively, a first terminal connectable to a first voltage source, a variable resistor having first and second connections, means for connecting the first connection of said variable resistor to said first terminal and the second connection of said variable resistor to the emitter of said first and third transistors, means for connecting second end of said variable resistor to the emitters of said second and fourth transistors, first and second diodes, means for connecting the anodes of said diodes to the emitters of said first and third transistors and to the emitters of said second and fourth transistors, respectively, means for connecting the cathodes of said diodes to ground, a second terminal connectable to a second voltage source, means for connecting the collectors of said first and second transistors to said second terminal, means for connecting the bases of said fifth and sixth transistors to said second terminal, first, second, third, and fourth resistors, a third terminal connectable to a third voltage source, means for connecting said first resistor between the emitter of said fifth transistor and said third terminal, means for connecting said second resistor between the base of said third transistor and said second terminal, means for connecting said third resistor between the base of said fourth transistor and said second terminal, means for connecting said fourth resistor between the emitter of said sixth transistor and said third terminal, first and second capacitoRs, means for connecting said first capacitor between the emitter of said fifth transistor and the base of said fourth transistor, means for connecting said second capacitor between the emitter of said sixth transistor and the base of said third transistor, a diode ring comprising a first, second, third, and fourth diode in series to form four junctions, the cathodes of said first and second diodes being connected at a first junction, the anodes of said third and fourth diodes being connected at a second junction, the cathode of said third diode and the anode of said first diode being connected at a third junction, the cathode of said fourth diode and the anode of said second diode being connected at a fourth junction, means for connecting said first junction to ground, means for connecting said third junction to the base of said third transistor, means for connecting said fourth junction to the base of said fourth transistor, means for connecting said second junction to said second terminal, an output terminal, and means for connecting said second junction to said output terminal.

Claim 18

PIM demodulator responsive to a PIM input signal apparatus comprising: first capacitor means, second capacitor means, means for alternately charging said first and second capacitor means to substantially the same predetermined voltage, means for alternately discharging said first and second capacitor means at a substantially constant discharge rate, means responsive to said PIM input signal for controlling said discharging means to generate a series of ramp waveforms alternately at said first and second capacitor means, said first and second capacitor means alternately charging and discharging, said ramp waveforms having time periods proportional in length to the semi-period lengths of the PIM input signal, means connected to said first and second capacitor means for providing a composite sawtooth waveform composed of alternatingly generated ramps, and means for averaging said composite sawtooth waveform to provide a demodulated output signal.

Claim 19

PIM demodulator responsive to a PIM input signal apparatus comprising: first capacitor means, second capacitor means, means for alternately charging said first and second capacitor means to substantially the same predetermined voltage, means for alternately discharging said first and second capacitor means at a substantially constant discharge rate, means responsive to said PIM input signal for controlling said discharging means to generate a series of ramp waveforms alternately at said first and second capacitor means, said first and second capacitor means alternately charging and discharging, said ramp waveforms having time periods proportional in length to the semi-period lengths of the PIM input signal, means connected to said first and second capacitor means for providing a composite sawtooth waveform composed of alternatingly generated ramps, and means for averaging said composite sawtooth waveform to provide a demodulated output signal.

Claim 20

Apparatus according to claim 15 wherein said charging means comprising: a voltage source, first and second diode means, first and second resistor means, means for alternately connecting in series a first branch comprising said voltage source, said first resistor means, said first capacitor means, and said first diode means, one end of said first diode means being connected to ground, and a second branch comprising said voltage source, said second capacitor means, said second resistor means and said second diode means, one end of said second diode means being connected to ground whereby said first and second capacitor means are alternately charged in a series RC circuit between said voltage source and ground.

Claim 21

Apparatus according to claim 16 wherein said means for alternately connecting in series said first and second branches comprises first and second transistors having their emitters connected between said first resistor means and said first capacitor means and between said second resistor means and said second capacitor means, respectively, and having their collectors connected to ground.

Claim 22

Apparatus according to claim 17 wherein said means for alternately discharging said first and second capacitor means comprises current source means.

Claim 23

Apparatus according to claim 18 wherein said means for controlling said discharging means comprises third and fourth transistors having their bases connected respectively to said first and second capacitor means and having their emitters connected to said constant current means, fifth and sixth transistors receiving said PIM input signal at the bases thereof and having their emitters connected to the emitters of said third and fourth transistors in a differential pair configuration.