Rms circuits with bipolar logarithmic converter

Claim 2

A bilateral logarithmic converter for a time varying input signal, said converter comprising in combination: means for generating from said input signal, for any polarity thereof, first output signal as a logarithm of said input signal, means for amplifying said first output signal by a fixed gain which is respectively negative and positive on separate channels, means for half-wave rectifying the signal of each of said channels so as to obtain substantially the anti-logs thereof in the form of currents having instantaneous values related to the square of said first input signal; means for summing the half-wave rectified currents from each of said channels, a constant current source, and charge storage means so connected to said source and to said means for summing that the potential at said charge storage means tends toward a value which will bring the long term average sum of said half-wave rectified currents into substantial equality with the constant current from said source.

Claim 3

A converter as defined in claim 1 wherein said means for generating comprises a high gain, inverting amplification stage including a pair of oppositely poled first semiconductor diode junctions each disposed in a respective feedback loop around said stage.

Claim 4

A converter as defined in claim 2 wherein each of said first junctions exhibit the property such that Eo C1 + K log I; where Ii is the absolute value of an input current to each first junction, Eo is the output voltage from each first junction and C1 and K are semiconductor constants, and wherein said means for half-wave rectifying comprises a pair of second semiconductor junctions each disposed for conduction in a respective one of said channels, each of said second junctions has conduction characterics such that where Ic is the current being conducted by each second junction, E1 is the voltage across each second junction, C2 and K are semiconductor constants.

Claim 5

A converter as defined in claim 2 including another feedback loop around said stage including a capacitor and means for feeding through said capacitor an inversion of the current flowing at the output of said stage.

Claim 6

A converter as defined in claim 4 wherein said means for amplifying comprises a pair of amplifiers, a first of which is inverting, the second of which is non-inverting, and wherein said means for feeding comprises said first amplifier.

Claim 7

A converter as defined in claim 1 wherein said fixed gain of said means for amplifying is a factor of 2.

Claim 8

A converter as defined in claim 1 wherein said current source provides a current poled to maintain said rectifying means in conduction.

Claim 9

A converter as defined in claim 1 including a temperature-compensating semiconductor having a junction disposed between said current source and said means for summing.

Claim 10

A converter as defined in claim 8 iNcluding a potentiometric amplifier having a gain inversely proportional to absolute temperature, the input of said potentiometric amplifier being connected to the output of said compensating transistor.

Claim 11

A converter as defined in claim 1 wherein said means for generating comprises a high gain, inverting amplification stage including a pair of first transistors of opposite conductivity type having their respective emitter-collector circuits in corresponding feedback loops around said stage, said first transistors being matched to have substantially identical conduction properties, and wherein said means for half-wave rectifying comprises a pair of second transistors of the same conductivity type each having its emitter-collector circuit disposed in a respective one of said channels, said second transistor being matched to exhibit substantially identical conduction properties.

Claim 12

A converter as defined in claim 10 wherein said summing means comprises a summing junction, said charge storage means comprises a capacitor connected between said summing junction and system ground, and wherein like output terminals of said second transistors are connected to one another and to said summing junction.

Claim 13

A converter as defined in claim 11 including a temperature compensating transistor of the same conductivity type as said second transistor, having its collector-emitter circuit connected between said current source and said summing junction, said current source being poled to provide a current for maintaining said temperature-compensating and second transistors in conduction.

Claim 14

A circuit for converting time-varying input signal, and comprising in combination means for generating two first output signals substantially 90* phase separated and proportional to said input signal, first and second means respectively responsive to corresponding ones of said first output signals each logarithmically related to the rms amplitude of said input signal; each of said first and second means including means for generating from the corresponding first output signal, a second output signal as a logarithm of said first output signal; means for amplifying said second output signals by a gain factor of 2, said factor being negative and positive respectively for the second output signal from one and the other of said first and second means; means for half-wave rectifying each of the amplified second output signals so as to obtain substantially the antilogs thereof in the form of output currents each having an instantaneous value related to the square of the respective second output signal; means for summing all of said output currents from said first and second means at a junction, a constant current source coupled to said junction, and charge storage means coupled to said junction.

Claim 15

A circuit for converting time-varying input signal, and comprising in combination means for generating two first output signals substantially 90* phase separated and proportional to said input signal, first and second means respectively responsive to corresponding ones of said first output signals each logarithmically related to the rms amplitude of said input signal; each of said first and second means including means for generating from the corresponding first output signal, a second output signal as a logarithm of said first output signal; means for amplifying said second output signals by a gain factor of 2, said factor being negative and positive respectively for the second output signal from one and the other of said first and second means; means for half-wave rectifying each of the amplified second output signals so as to obtain substantially the antilogs thereof in the form of output currents each having an instantaneous value related to the square of the respective second output signal; means for summing all of said output currents from said first and second means at a junction, a constant current source coupled to said junction, and charge storage means coupled to said junction.