US3681615A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Split output circuit for a logic gate
Assignee: Unisys Corp
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Filing: 1971-08-09
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Granted: 1972-08-01
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Expires: 1991-08-09
Abstract
Abstract A transistor-transistor-logic circuit includes an input stage transistor, a phase-splitter element, a grounded emitter element, and an active pull-up circuit, wherein the active pull-up and grounded emitter stage outputs are split to allow wire OR-ing by tying together either the emitters of like outputs of active pull-up elements, or the collectors of grounded emitter elements, or both, or normal operation by tying together emitters and collectors.
Inventors
- 👤 Vincent C Ricci
- 👤 William F Simon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/0175; H03K19/018; H03K19/01806
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
212 words
A logic circuit comprising, a phase splitting transistor circuit having base, collector and emitter electrodes, a signal input connection to said base electrode adapted for connection to a bivalued input signal source, separate impedance means connecting the collector and emitter electrodes of said phase splitting transistor to respective reference potentials, a first output transistor circuit including base, emitter and collector electrodes, means connecting the base electrode of said first output transistor circuit to the emitter of said phase splitting transistor circuit, a first load connecting the collector of said first output transistor to a source of reference potential, a second output transistor circuit having base, collector and emitter electrodes, means connecting the base electrode of said second output transistor circuit to the collector electrode of said phase splitting transistor, and a second load connecting the emitter of the second output transistor circuit to a reference potential, all of said transistors being of the type to cause a high current to flow through said first load in response to the application of an input signal of one value to the signal input connection of the phase splitter circuit and through the other load in response to an input signal of a second value to the signal input connection of the phase splitter circuit.
Claim 2
Dependent Claim
212 words
A logic circuit comprising, a phase splitting transistor circuit having base, collector and emitter electrodes, a signal input connection to said base electrode adapted for connection to a bivalued input signal source, separate impedance means connecting the collector and emitter electrodes of said phase splitting transistor to respective reference potentials, a first output transistor circuit including base, emitter and collector electrodes, means connecting the base electrode of said first output transistor circuit to the emitter of said phase splitting transistor circuit, a first load connecting the collector of said first output transistor to a source of reference potential, a second output transistor circuit having base, collector and emitter electrodes, means connecting the base electrode of said second output transistor circuit to the collector electrode of said phase splitting transistor, and a second load connecting the emitter of the second output transistor circuit to a reference potential, all of said transistors being of the type to cause a high current to flow through said first load in response to the application of an input signal of one value to the signal input connection of the phase splitter circuit and through the other load in response to an input signal of a second value to the signal input connection of the phase splitter circuit.
Claim 3
Dependent Claim
42 words
A logic network comprising a plurality of logic circuits as set forth in claim 1 wherein said first and second loads are connected in common to the respective first and second output transistors of each of the logic circuits comprising the network.
Claim 4
Dependent Claim
34 words
A logic network comprising a plurality of logic circuits as set forth in claim 1 wherein the corresponding output transistors of at least two of said logic circuits are connected to a common load.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-01 | 1976-01-31 | 1976-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-01 | 1980-01-31 | 1980-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-01 | 1984-01-31 | 1984-08-01 | $7700.00 | Window Closed / Lapsed |