US3680091A
Expired / Lapsed
US
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Pulse train framing and intermediate pulse spacing accuracy test circuit
Assignee: Collins Radio Co
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Filing: 1970-07-21
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Granted: 1972-07-25
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Expires: 1990-07-21
Abstract
Abstract A coded pulse train tolerance check is provided by utilizing the first of a train of input pulses to activate a timing clock pulse source. Pulses in the input train bearing a predetermined time coincidence with the clock pulses are used to set a shift register. The transfer action of the register is also under timing clock control. At the conclusion of a decoding cycle, the code word defined by the input pulse train is stored in the register only if each pulse in the input train is present and in its assigned time-space position with respect to the initial one of the input pulses.
Inventors
- 👤 Kenneth R Rutherford
- 👤 Arthur C Strebe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:38
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/74; G01S13/76; G01S13/78; G01S13/781; G01S13/784
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
326 words
Means for determining the accuracy of a pulse train comprised of a first pulse and a predetermined number of successive pulses, the nominal time occurrences of said successive pulses with respect to said first pulse being integral multiples of a predetermined time interval, said means comprising a source of clock pulses the cyclic rate of which defines a time interval equal that of said predetermined time interval, means responsive to said first one of said train of input pulses to activate said clock source, means responsive to the first and successive ones of said train of input pulses to generate a first timing pulse of predetermined pulse width the time occurrence of which occurs a predetermined time interval after the initiation and within the time duration of each of said input pulses, means for generating a second timing pulse in response to successive ones of said clock pulses, the initiation of said second timing pulse occurring a predetermined period of time prior to that of nominal ones of said first timing pulses and the termination of said second timing pulse occurring a predetermined period of time after that of nominal ones of said first timing pulses, coincidence gating means receiving said first and second timing pulses, shift register means receiving the output from said coincidence gating means as setting inputs to the first stage thereof, said shift register means receiving the output from said clock source as a shift input, and means connected to the last of the stages of said shift register to deactivate said clock source upon said first pulse in said input pulse train being transferred to the last stage of said shift register, whereby said input pulse train is stored in said shift register at the completion of the aforedefined decoding cycle only upon the first and successive ones of the pulses of said input train occurring within a predetermined time tolerance of an associated integral multiple of said predetermined time interval.
Claim 2
Dependent Claim
326 words
Means for determining the accuracy of a pulse train comprised of a first pulse and a predetermined number of successive pulses, the nominal time occurrences of said successive pulses with respect to said first pulse being integral multiples of a predetermined time interval, said means comprising a source of clock pulses the cyclic rate of which defines a time interval equal that of said predetermined time interval, means responsive to said first one of said train of input pulses to activate said clock source, means responsive to the first and successive ones of said train of input pulses to generate a first timing pulse of predetermined pulse width the time occurrence of which occurs a predetermined time interval after the initiation and within the time duration of each of said input pulses, means for generating a second timing pulse in response to successive ones of said clock pulses, the initiation of said second timing pulse occurring a predetermined period of time prior to that of nominal ones of said first timing pulses and the termination of said second timing pulse occurring a predetermined period of time after that of nominal ones of said first timing pulses, coincidence gating means receiving said first and second timing pulses, shift register means receiving the output from said coincidence gating means as setting inputs to the first stage thereof, said shift register means receiving the output from said clock source as a shift input, and means connected to the last of the stages of said shift register to deactivate said clock source upon said first pulse in said input pulse train being transferred to the last stage of said shift register, whereby said input pulse train is stored in said shift register at the completion of the aforedefined decoding cycle only upon the first and successive ones of the pulses of said input train occurring within a predetermined time tolerance of an associated integral multiple of said predetermined time interval.
Claim 3
Dependent Claim
182 words
Means as defined in claim 1 wherein said means to generate said first timing pulse comprises a first monostable multivibrator responsive to the initiation of each of said input pulses to initiate an output pulse of a predetermined time duration, a second monostable multivibrator receiving the output pulse from said first monostable multivibrator and being responsive to the trailing edge thereof to initiate an output pulse of predetermined time duration, said output pulse being applied as a first input to said coincidence gating means, said means for generating said second timing pulse comprising gating means receiving the output from said first monostable multivibrator and being activated thereby, the output of said gating means being applied to and initiating the operation of said clock means, time delay means receiving the output from said clock means and applying an output to a third monostable multivibrator, said delay means introducing a predetermined time delay, said multivibrator producing a pulse width of predetermined time duration, and the output from said third monostable multivibrator means being applied as a gating input pulse to said coincidence gating means.
Claim 4
Dependent Claim
37 words
Means as defined in claim 1 wherein said shift register comprises a plurality of stages defined as N + 1, where N is an integer defining the predetermined number of pulse intervals in said input pulse train.
Claim 5
Dependent Claim
77 words
Means as defined in claim 2 wherein said gating means comprises a bistable multivibrator, said output from said first monostable multivibrator setting said bistable multivibrator to a first conductive state, the output from the last stage of said shift register being applied to said bistable multivibrator to reset said multivibrator to a second conductive state, and said clock means being responsive to said first conductive state of said bistable multivibrator to initiate a train of timing impulses.
Claim 6
Dependent Claim
58 words
MEans as defined in claim 1 further comprising readout means connected to said shift register and being responsive to the binary word entered into said shift register at the termination of said decoding cycle to indicate the proper occurrence and time spacing with respect to the first one of said input pulses in the input pulse train applied.
Claim 7
Dependent Claim
58 words
Means as defined in claim 4 further comprising readout means connected to said shift register and being responsive to the binary word entered into said shift register at the termination of said decoding cycle to indicate the proper occurrence and time spacing with respect to the first one of said input pulses in the input pulse train applied.
Claim 8
Dependent Claim
82 words
Means as defined in claim 4 wherein the trailing edges of the output pulses from said first monostable multivibrator are selectively variable in time with respect to the leading edges thereof, the trailing edge of the pulses from said second monostable multivibrator being selectively adjustable as to time occurrence with respect to the initial edges thereof, and said delay means being adapted to introduce a selectively variable time delay to said clock source pulses as applied to said third monostable multivibrator means.
References Cited (Backward Citations)
US2975404A
Cited
US3040260A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |