Optical logic function generator

Claim 2

An optical logic element having a plurality of input means adapted to receive an input signal representative of at least one digit having assigned thereto first and second states indicative respectively of the presence or absence of that digit, said logic element comprising: light emitting means responsive to an input signal for establishing a separate light beam for each state possible for the given digit of said input signal; light sensing means spaced from the light emitting means and positioned to receive a light beam from every emitting means, said sensing means characterized as having two states with one state associated with the incidence of light thereon and the other state associated with the absence of light thereon, each state being representative of output signals capable of being detected at an output of said sensing means; and means passing and/or blocking selected light beams between the light emitting means and the sensing means for logically modifying the input signal to a different output signal at the output of said sensing means.

Claim 3

An optical logic element in accordance with claim 1 wherein: said light emitting means comprises at least a pair of light emitters with one emitter assigned to emit light for one binary state of said input signal and the other emitter of said pair assigned to emit light for the other possible binary state of said input signal.

Claim 4

An optical logic element in accordance with claim 2 wherein: said sensing means comprises a pair of sensors and means connecting them in a series electrical circuit between a point of common reference potential and said output of said sensing means.

Claim 5

An optical logic element in accordance with claim 1 wherein: said interposed means comprises a mask having opaque or transmissible areas at the points of intersection of said light beams with said mask.

Claim 6

An optical logic element in accordance with claim 2 and further comprising: a first plurality of said light emitter pairs with each pair assigned a digit position for each digit of a first multi-digit input signal.

Claim 7

An optical logic element in accordance with claim 5 and further comprising: a second and third plurality of said light emitter pairs with each pair assigned a digit position for each digit of a second and third multi-digit input signal respectively.

Claim 8

An optical logic element in accordance with claim 6 wherein said interposed means logically performs arithmetic manipulations of said first, second and third input signals.

Claim 9

An optical logic element in accordance with claim 7 wherein: said sensing means comprises a plurality of rows of light sensors, each row comprises at least a pair of sensors and means connecting them in a series electrical circuit between a point of common potential and said output of said sensing means.

Claim 10

An optical logic element in accordance with claim 8 wherein said sensing means further comprises: a plurality of output terminals, one terminal each of said plurality connected in one series circuit each of said rows of sensor pairs, each of said output terminals being associated with one digit position of a multi-digit output signal.

Claim 11

An optical logic element in accordance with claim 9 and further comprising at least four sensors connected in series in each of said rows.

Claim 12

An optical lOgic element in accordance with claim 10 wherein each input means receives a binary input signal and further characterized in that each given output terminal, En, where n is any given bit position, has an output signal equation: wherein A, B and C are the nth bit of said first, second and third binary input signals, and each term in parenthesis is associated with one each of said sensors in the nth row.

Claim 13

An optical logic element in accordance with claim 11 wherein said interposed means comprises: a mask having light transmitting and light blocking areas at the intercepts of said light beams as defined by De Morgan''s theorem of the output equation of claim 11.

Claim 14

An optical logic element in accordance with claim 10 and further comprising at least six sensors connected in series in each of said rows, and: a plurality of control emitters each of which is associated with a given sensor only in all of said rows and is adapted to selectively emit light on said given sensors.

Claim 15

An optical logic element in accordance with claim 13 and further characterized in that each given output terminal, En, where n is any given bit position has an output equation: wherein A, B and C are the nth bit of said first, second and third binary input signals in accordance with conventional logic terminology, each term in parenthesis is associated with one each of said sensors, and ''''I'''' is a control emitter associated with the sensor of the term in parenthesis.

Claim 16

An optical logic element in accordance with claim 14 and further characterized in that said interposed means comprises: a mask having light transmitting and light blocking areas at the intercepts of said light beams as defined by De Morgan''s theorem of the output equation of claim 14.

Claim 17

An optical logic element in accordance with claim 15 and further characterized in that: light emitted from any given control emitter removes its associated term in parenthesis from the output equation.

Claim 18

An optical logic element in accordance with claim 14 and further comprising: gating means for selectively disabling any given row of emitters from a row of emitter pairs.

Claim 19

An optical logic element in accordance with claim 17 wherein: any disabled row of emitters removes the associated term from said output equation of claim 14.

Claim 20

An optical logic element in accordance with claim 18 and further comprising: means emitting light from control emitters I1, I2, I3, I4, I6 and the emitter pairs associated with the binary input term A or B to provide an arithmetic shift for the binary input term A or B.

Claim 21

An optical logic element in accordance with claim 19 wherein each binary input signal has a least and a most significant bit position, and further comprising: an additional control emitter associated only with a sensor in each row identifying the least and most significant bit positions; and means selectively causing said additional emitter to emit light for shifting out either the least or the most significant bit of any given binary input signal.

Claim 22

An optical logic element in accordance with claim 3 wherein: each of said sensing means assumes said second state upon incidence of a light beam from either one of said input means.

Claim 23

An optical logic element in accordance with claim 4 wherein: each of said sensing means comprises a logical OR gate in response to any light beams from said plurality of input means.

Claim 24

An optical logic element in accordance with claim 5 wherein: said connecting means comprises a logical AND gate for supplying an output signal for said sensing means only upon coincidence of light beams on both of said sensors.

Claim 25

An optical logic element in accordance with claim 2 and further comprising: means for selectively energizing eitHer one of said pair of light emitters.

Claim 26

An optical logic element in accordance with claim 2 and further comprising: means for simultaneously energizing both emitters of said pair.

Claim 27

An optical logic element in accordance with claim 1 wherein said interposed means comprises: an optical mask means having light transmissible or light blocking areas positioned at the interception points of said beams and said mask.

Claim 28

An optical logic element in accordance with claim 26 wherein: said plurality of input means equals n, where n is any whole number greater than one; said sensing means comprises a plurality of light sensors equal to m, where m is any whole number greater than one; and said mask means includes mn areas.

Claim 29

An optical logic element in accordance with claim 26 wherein: said mask means comprises a plurality of interchangeable masks each having different configurations of light transmissible and light blocking areas for performing selectively different logical modifications of said binary input signal.

Claim 30

An optical logic element located in a housing comprising: at least one pair of light emitters with one emitter assigned one binary value when emitting light and the other emitter assigned the opposite binary value when emitting light; at least a pair of light sensors spaced away from the emitter pair so as to define pairs of light paths between each emitter and said sensor pair; means electrically connecting said sensors in series; and an optical mask between the emitter and sensor pairs having selected areas of the mask positioned to intercept the light paths and define logic functions for said element in accordance with selective opaque or transmissible areas at said path intercepts.

Claim 31

An optical logic element located in a housing comprising: at least one pair of light emitters with one emitter assigned one binary value when emitting light and the other emitter assigned the opposite binary value when emitting light; at least a pair of light sensors spaced away from the emitter pair so as to define pairs of light paths between each emitter and said sensor pair; means electrically connecting said sensors in series; and an optical mask between the emitter and sensor pairs having selected areas of the mask positioned to intercept the light paths and define logic functions for said element in accordance with selective opaque or transmissible areas at said path intercepts.

Claim 32

An optical logic element in accordance with claim 29 and further comprising: a plurality of interchangeable masks each of which have different configurations of opaque or transmissible areas at said path intercepts for logically modifying the logic functions for said element.

Claim 33

A universal logic element comprising: at least one pair of light emitters housed in an optical housing; at least one pair of sensors spaced away from said emitter in said housing to define a pair of light paths from each emitter to both sensors; means electrically connecting said sensors in a series circuit between a point of common reference potential and an output terminal; and a mask positioned between said emitters and said sensors having light transmissible areas at the points of intercept of said light paths for defining a logical OR function which applies said common potential to said output terminal when light shines on both sensors from either one of said pair of light emitters.

Claim 34

A universal logic element comprising: at least one pair of light emitters housed in an optical housing; at least one pair of sensors spaced away from said emitter in said housing to define a pair of light paths from each emitter to both sensors; means electrically connecting said sensors in a series circuit between a point of common reference potential and an output terminal; and a mask positioned between said emitters and said sensors having light transmissible areas at the points of intercept of said light paths for defining a logical OR function which applies said common potential to said output terminal when light shines on both sensors from either one of said pair of light emitters.

Claim 35

A universal logic element comprising: at least one light emitter housed in a housing; at least one pair of sensors spaced away from said emitter in said housing to define a pair of light paths with one each of said light paths from said emitter to one each of said sensors; means electrically connecting said sensors in series between a point of common potential and an output terminal, and a mask positioned between the emitter and pair of sensors with light transmissible areas at the point of intercept of said light paths for defining a logical AND function which applies said common potential to said output terminal when light shines from said emitter on both of said sensors.

Claim 36

A universal logic element comprising: at least one light emitter housed in a housing; at least one pair of sensors spaced away from said emitter in said housing to define a pair of light paths with one each of said light paths from said emitter to one each of said sensors; means electrically connecting said sensors in series between a point of common potential and an output terminal, and a mask positioned between the emitter and pair of sensors with light transmissible areas at the point of intercept of said light paths for defining a logical AND function which applies said common potential to said output terminal when light shines from said emitter on both of said sensors.

Claim 37

In an optical logic apparatus, the combination which comprises: a plurality of spaced light emitters for emitting light when energized; a plurality of spaced independent light sensors for providing output signals when illuminated with light so that the output signals from more than one sensor may be simultaneously detected; an optical mask defining a plurality of discrete areas with each area uniquely associated with one emitter and one sensor and being either substantIally opaque or transparent to include or exclude terms from a logic operation to be performed by said optical logic apparatus; means for transmitting a beam of light from each of the emitters, when energized, to the areas of the mask associated with the energized emitter; and means selectively energizing at least two emitters simultaneously for defining certain terms in the logic operation to be performed by said optical logic apparatus.

Claim 38

In an optical logic apparatus, the combination which comprises: a plurality of spaced light emitters for emitting light when energized; a plurality of spaced independent light sensors for providing output signals when illuminated with light so that the output signals from more than one sensor may be simultaneously detected; an optical mask defining a plurality of discrete areas with each area uniquely associated with one emitter and one sensor and being either substantIally opaque or transparent to include or exclude terms from a logic operation to be performed by said optical logic apparatus; means for transmitting a beam of light from each of the emitters, when energized, to the areas of the mask associated with the energized emitter; and means selectively energizing at least two emitters simultaneously for defining certain terms in the logic operation to be performed by said optical logic apparatus.

Claim 39

An optical logic element having input means adapted to receive an input signal representative of a term present in a logic operation which term has assigned thereto first and second states indicative respectively of the presence or absence of that term, said logic element comprising: a pair of light emitters assigned to each term of the logic operation; means for establishing a separate light beam from one emitter of each pair for each of the two states possible for the given term received at its associated emitter pair; light sensing means spaced from the light emitter means and positioned to receive a light beam from every emitter, said sensing means responsive to light thereon for assuming a different state than the sensing means possesses in the absence of light thereon, said sensing means operative in response to said light beams for emitting a predetermined logical output signal at an output term of said sensing means; and means passing and/or blocking selected light beams from the light emitters to the sensing means for including in the output signal from the sensing means only certain selected logically modified terms of said input signal.

Claim 40

An optical logic element having input means adapted to receive an input signal representative of a term present in a logic operation which term has assigned thereto first and second states indicative respectively of the presence or absence of that term, said logic element comprising: a pair of light emitters assigned to each term of the logic operation; means for establishing a separate light beam from one emitter of each pair for each of the two states possible for the given term received at its associated emitter pair; light sensing means spaced from the light emitter means and positioned to receive a light beam from every emitter, said sensing means responsive to light thereon for assuming a different state than the sensing means possesses in the absence of light thereon, said sensing means operative in response to said light beams for emitting a predetermined logical output signal at an output term of said sensing means; and means passing and/or blocking selected light beams from the light emitters to the sensing means for including in the output signal from the sensing means only certain selected logically modified terms of said input signal.