Serial digital pulse phase interface driver and receiver

Claim 2

In combination with a transmission system for transmitting and receiving digital data in the form of bits in a serial manner wherein the transmitting means receives the data to be transmitted in parallel form and converts it to series form before placing it on a transmission medium and the receiver means converts the data received into parallel form before delivering it to its output, the improvement which comprises: driver logic means connected to the output of said transmitter means and to the transmission medium for generating, for each bit received from said transmitter, a bipolar pulse having positive and negative portions of equal amplitude and time and having a phase which is indicative of whether the bit received is a logic one or a logic zero; and time window filter means connected to the transmission medium and said receiver means for receiving the bipolar pulses, examining the time relationship between the positive and negative portions of the pulses on the transmission line to determine whether a valid signal has been received, and examining the phase of a received valid signal to determine whether the signal represents a logic one or a logic zero.

Claim 3

The improved digital data transmission system of claim 1 wherein said driver logic means comprises: four NAND gates connected together in parallel into first and second pairs; and a transformer having its secondary winding connected to the transmission medium and having said NAND gates connected to its primary winding.

Claim 4

The improved digital data transmission system of claim 2 wherein said transformer comprises: a primary winding with three taps, a first and second outside tap and a center tap, the first outside tap connected to the first pair of NAND gates and the second outside tap connected to the second pair of NAND gates, the center tap being connected to a power source.

Claim 5

The improved digital data transmission system of claim 2 wherein said time window filter means comprises: a plurality of multivibrators connected to the transmission medium; and logic circuit means connected to said multivibrators for delivering logic data and clock output pulses in response to said multivibrators.

Claim 6

The improved data transmission system of claim 4 wherein said multivibrators comprise: a pair of one-shot multivibrators connected together in a cross-coupled manner.

Claim 7

A compact, low power transmission system for transmitting and receiving digital data in a serial manner, having a transmitter connected to one end of a transmission medium and a receiver on the other end of the transmission medium, said system comprising: a transmitting shift register for receiving the data to be transmitted; a control counter connected to said shift register for enabling said register so that the data to be transmitted is loaded into said register, and for controlling the length of the transmit cycle in response to the extent of loading of said shift register; a parity generator connected to said shift register and said control counter, responsive to said control counter to generate a parity bit at the end of the transmit cycle; driver logic means connected to said shift register, responsive to the pulse output of said serial register to place bipolar pulses having positive and negative portions of predetermined time and phase relationship on the sending end of the transmission medium; a gated three phase oscillator connected to said shift register, control counter, parity generator and driver logic for supplying timing pulses to said shift register, control counter, parity generator and driver logic; and time window filter means connected to the receiving end of the transmission medium for decoding and filtEring the received digital data by examining the time relationship of the positive and negative portions of the bipolar pulses and blocking all signals which do not correspond to the predetermined time relationship and by examing the phase relationship of the positive and negative portions of the bipolar pulses to decode the data; a receiving shift register connected to said time window filter means and responsive thereto to receive the decoded digital data; output gating connected to said shift register for removing data stored in said receiving shift register in response to an output enable signal; a parity check circuit connected to said time window filter means, and said output gating for determining whether an error has occurred during transmission.

Claim 8

A compact, low power transmission system for transmitting and receiving digital data in a serial manner, having a transmitter connected to one end of a transmission medium and a receiver on the other end of the transmission medium, said system comprising: a transmitting shift register for receiving the data to be transmitted; a control counter connected to said shift register for enabling said register so that the data to be transmitted is loaded into said register, and for controlling the length of the transmit cycle in response to the extent of loading of said shift register; a parity generator connected to said shift register and said control counter, responsive to said control counter to generate a parity bit at the end of the transmit cycle; driver logic means connected to said shift register, responsive to the pulse output of said serial register to place bipolar pulses having positive and negative portions of predetermined time and phase relationship on the sending end of the transmission medium; a gated three phase oscillator connected to said shift register, control counter, parity generator and driver logic for supplying timing pulses to said shift register, control counter, parity generator and driver logic; and time window filter means connected to the receiving end of the transmission medium for decoding and filtEring the received digital data by examining the time relationship of the positive and negative portions of the bipolar pulses and blocking all signals which do not correspond to the predetermined time relationship and by examing the phase relationship of the positive and negative portions of the bipolar pulses to decode the data; a receiving shift register connected to said time window filter means and responsive thereto to receive the decoded digital data; output gating connected to said shift register for removing data stored in said receiving shift register in response to an output enable signal; a parity check circuit connected to said time window filter means, and said output gating for determining whether an error has occurred during transmission.

Claim 9

The transmission system of claim 6 wherein said logic means comprises: four NAND gates connected together in parallel into first and second pairs; and a transformer having its secondary winding connected to the transmission medium and having said NAND gates connected to its primary winding.

Claim 10

The transmission system of claim 7 wherein said time window filter means comprises: a plurality of multivibrators connected to the transmission medium between the positive and negative pulses received on the transmission; and logic circuit means connected to said multi-vibrators for delivering logic and clock output pulses in response to said multivibrators.

Claim 11

The transmission system of claim 8 wherein said multivibrators comprise: a pair of one-shot multivibrators connected together in a cross-coupled manner.