US3679937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of and apparatus for blocking phase-comparison protection
Assignee: NOVOCHERKASSKY ORDENS TRUDOVOGO KRASNOGO ZNAMENI POLITEKHMICHESKY INST IMENI SERGO ORDZHONIKIDZE
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Filing: 1970-11-24
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Granted: 1972-07-25
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Expires: 1990-11-24
Abstract
Abstract The invention is related to a method of and an apparatus for the blocking of phase-comparison protection. According to the invention, the method consists in that the control signals formed from separately summed incoming and outgoing currents are monitored during a predetermined time interval since the very beginning of the first half-cycle of a fault and a blocking signal is applied to the starting element of the protection apparatus only when both these signals are present, thereby preventing the protected plant from being disconnected on an external short-circuit. The method ensures reliable selectivity and cuts down operate time of the protection.
Inventors
- 👤 Evgeny Mefodievich Ulyanitsky
- 👤 Eduard Vasilievich Podgorny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:58
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/26; H02H3/265
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
236 words
An apparatus for blocking phase-comparison protection, incorporating: intermediate transformers connected in the arms of the protected plant; a differential starting element connected in the arms of the protection apparatus via another intermediate transformer; a phase-comparison element incorporating OR, AND, INHIBIT, NOR and memory logic circuits, relay elements responding to incoming and outgoing currents, a slow-to-reset relay and a slow-to-operate relay; another INHIBIT gate connected to said differential starting element; the inputs of said relay elements responding to incoming and outgoing currents being connected to said intermediate transformers connected in the arms of the protected plant, the outputs of these relays being connected to the inputs of the OR and AND gates, the output of said AND gate being in turn connected to one of the inputs of the INHIBIT gate, the output of said OR gate being connected to the input of said slow-to-reset relay the output of which is connected to the input of said slow-to-operate relay and to the input of the NOR gate, the output of said slow-to-operate relay being connected to the other input of said INHIBIT gate, the output of the NOR gate being connected to one of the inputs of said memory logic, the other input of which is connected to the output of said INHIBIT gate and the output of said memory logic is connected to inhibiting input of the other INHIBIT gate connected to said differential starting element.
Claim 2
Independent Claim
236 words
An apparatus for blocking phase-comparison protection, incorporating: intermediate transformers connected in the arms of the protected plant; a differential starting element connected in the arms of the protection apparatus via another intermediate transformer; a phase-comparison element incorporating OR, AND, INHIBIT, NOR and memory logic circuits, relay elements responding to incoming and outgoing currents, a slow-to-reset relay and a slow-to-operate relay; another INHIBIT gate connected to said differential starting element; the inputs of said relay elements responding to incoming and outgoing currents being connected to said intermediate transformers connected in the arms of the protected plant, the outputs of these relays being connected to the inputs of the OR and AND gates, the output of said AND gate being in turn connected to one of the inputs of the INHIBIT gate, the output of said OR gate being connected to the input of said slow-to-reset relay the output of which is connected to the input of said slow-to-operate relay and to the input of the NOR gate, the output of said slow-to-operate relay being connected to the other input of said INHIBIT gate, the output of the NOR gate being connected to one of the inputs of said memory logic, the other input of which is connected to the output of said INHIBIT gate and the output of said memory logic is connected to inhibiting input of the other INHIBIT gate connected to said differential starting element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |