Two phase encoder system for three frequency modulation

Claim 2

An improved encoder for translating an input NRZ data waveform into a self-clocking three frequency waveform using a first phase signal having pulses which occur only at the boundaries of the bit intervals of said NRZ data waveform and a second phase signal having pulses which occur only within said bit intervals, said encoder comprising: a clocked bistable storage device, including a CLOCK input for receiving pulses of said first phase signal and a DATA input for receiving said input NRZ waveform, said storage device being conditioned by said pulses of said first phase signal to produce a data signal waveform and the complement of said data signal waveform, each being delayed by one bit interval to said input NRZ waveform; a first gate connected to receive said data signal waveform and pulses of said second phase signal, said first gate being operative to pass a pulse of said second phase signal when said data signal waveform is in a state representing that a binary ONE occurred within a bit interval of said input NRZ waveform; a second gate connected to receive the complement of said data signal wavefoRm, the complement of said input NRZ waveform and said first phase signal, said second gate being operative to pass a pulse of said first phase signal when said waveforms are in the same states representing that said input NRZ waveform includes two successive binary ZEROS; and, a complementing bistable output device connected to said first and second gates and being conditioned to switch state to produce said self-clocking waveform in which transitions occur when there are ONES and between the boundaries between successive ZEROS.

Claim 3

The encoder of claim 1 wherein said storage devices are D type flip-flops and said gates are NAND gates.

Claim 4

An encoder for translating bits of data stream waveform generated at a rate of N bits/sec. into a three frequency self-clocking waveform characterized as having bit intervals comprising: a two phase clock for generating first and second phases of pulses from an input clock waveform of 2N pulses/sec. to have a predetermined phase relationship to said information bits wherein the pulses of said first phase occur at the boundaries between said bits and the pulses of said second phase occur within said bits; a clocked two state storage device including a CLOCK input for receiving pulses of said first phase and a DATA input for receiving said data stream waveform, said storage device connected to be switched at the trailing edge of each of said pulses of said first phase between its two states in accordance with said data stream waveform applied to said DATA input to provide a data signal and the complement of said data signal, each delayed by one bit interval from said data stream waveform; a first gate including means for receiving said data signal and pulses of said second phase, said gate being adapted to pass a pulse of said second phase when said data stream waveform is in a state representative of a binary ONE; a second gate including means for receiving said pulses of said first phase, the complement of said data signal and the complement of said input data stream waveform, said second gate being conditioned to pass a pulse of said first phase when said data stream waveform is in a binary zero state for more than two successive pulses of said first phase as defined by the complements of both said data signal and said data stream waveform being in the same state; a third gate coupled to said first and second gates; and, a complementing two state storage device coupled to said third gate and being conditioned by pulses of said first and said secOnd phase to generate said three frequency self-clocking waveform coded so as to have transitions corresponding to a binary ONE at the center of said bit intervals and transitions at the boundaries of said bit intervals between two successive binary ZEROS.

Claim 5

An encoder for translating bits of data stream waveform generated at a rate of N bits/sec. into a three frequency self-clocking waveform characterized as having bit intervals comprising: a two phase clock for generating first and second phases of pulses from an input clock waveform of 2N pulses/sec. to have a predetermined phase relationship to said information bits wherein the pulses of said first phase occur at the boundaries between said bits and the pulses of said second phase occur within said bits; a clocked two state storage device including a CLOCK input for receiving pulses of said first phase and a DATA input for receiving said data stream waveform, said storage device connected to be switched at the trailing edge of each of said pulses of said first phase between its two states in accordance with said data stream waveform applied to said DATA input to provide a data signal and the complement of said data signal, each delayed by one bit interval from said data stream waveform; a first gate including means for receiving said data signal and pulses of said second phase, said gate being adapted to pass a pulse of said second phase when said data stream waveform is in a state representative of a binary ONE; a second gate including means for receiving said pulses of said first phase, the complement of said data signal and the complement of said input data stream waveform, said second gate being conditioned to pass a pulse of said first phase when said data stream waveform is in a binary zero state for more than two successive pulses of said first phase as defined by the complements of both said data signal and said data stream waveform being in the same state; a third gate coupled to said first and second gates; and, a complementing two state storage device coupled to said third gate and being conditioned by pulses of said first and said secOnd phase to generate said three frequency self-clocking waveform coded so as to have transitions corresponding to a binary ONE at the center of said bit intervals and transitions at the boundaries of said bit intervals between two successive binary ZEROS.

Claim 6

The encoder of claim 3 wherein all of said gates are NAND gates.

Claim 7

The encoder of claim 3 wherein said clocked storage device and said complementing storage device are D type flip-flops.

Claim 8

The encoder of claim 3 further including a data shift register connected to receive said pulses of said first phase and being conditioned thereby to apply the bits of said data stream waveform to said DATA input of said clocked flip-flop so as to establish said predetermined phase relationship between said bits and the pulses of said first and second phases.

Claim 9

The encoder of claim 3 wherein said two phase clock includes a complementing bistable storage device connected to receive said input clock waveform and for generating a pair of complementary outputs; first and second gates, each being coupled to receive said input clock waveform and a different one of said complementary outputs, said first and second gates being conditioned thereby to generate pulses of said first and second phase signals respectively.

Claim 10

The encoder of claim 7 wherein said bistable device is a D type flip-flop and said gates are NAND gates.

Claim 11

An improved encoder for translatiNg bits of a data stream waveform F1 having a rate of N bits/sec. into a self-clocking waveform comprising: a two phase clock generator for generating pulses of first and second phases 01 and 02 in response to a clock input signal of a rate of 2N pulses/sec. so as to have the 01 pulses coincide with the boundaries of said bits and the 02 pulses coincide with the centers of said bits; a clocked bistable device, including a CLOCK input for receiving said 01 pulses and a DATA input for receiving said data waveform F1, said bistable device being conditioned by said waveform F1 to be switched at the trailing edge of said 01 pulses to produce a waveform F2 and its complement F2, each being delayed by a bit interval to said waveform F1; a first gate for receiving said waveform F2 and said 02 pulses, said gate being enabled to produce an output F3 in accordance with the expression F3 F2.02; a second gate for receiving the complement of said waveform, F2, the complement said waveform F1 and said 02 pulses, said gate being enabled to produce an output F4 in accordance with the expression F4 F1.F2.01; and, a complementing output bistable device including a gate connected to said first and second gates for applying a complementing input F5 thereto in accordance with the expression F5 F3+F4, said bistable device being conditioned thereby to switch state during a bit interval when there is a ONE and between bit intervals when there are two successive ZEROS in said data stream waveform.

Claim 12

An improved encoder for translatiNg bits of a data stream waveform F1 having a rate of N bits/sec. into a self-clocking waveform comprising: a two phase clock generator for generating pulses of first and second phases 01 and 02 in response to a clock input signal of a rate of 2N pulses/sec. so as to have the 01 pulses coincide with the boundaries of said bits and the 02 pulses coincide with the centers of said bits; a clocked bistable device, including a CLOCK input for receiving said 01 pulses and a DATA input for receiving said data waveform F1, said bistable device being conditioned by said waveform F1 to be switched at the trailing edge of said 01 pulses to produce a waveform F2 and its complement F2, each being delayed by a bit interval to said waveform F1; a first gate for receiving said waveform F2 and said 02 pulses, said gate being enabled to produce an output F3 in accordance with the expression F3 F2.02; a second gate for receiving the complement of said waveform, F2, the complement said waveform F1 and said 02 pulses, said gate being enabled to produce an output F4 in accordance with the expression F4 F1.F2.01; and, a complementing output bistable device including a gate connected to said first and second gates for applying a complementing input F5 thereto in accordance with the expression F5 F3+F4, said bistable device being conditioned thereby to switch state during a bit interval when there is a ONE and between bit intervals when there are two successive ZEROS in said data stream waveform.

Claim 13

The encoder of claim 9 wherein said storage devices are D type flip-flops and said gates are NAND gates.

Claim 14

The encoder of claim 9 further including a data shift register connected to receive said 01 pulses and being conditioned thereby to apply the bits of said data waveform to said DATA input so as to establish said coincidence between said boundaries and centers of said bits and said 01 and 02 pulses.

Claim 15

The encoder of claim 9 wherein said two phase clock generator includes a complementing bistable storage device connected to generate a pair of complementing outputs from said clock input signal and first and second gates connected to receive said clock input signal and a different one of said complementary outputs, said first and second gates being conditioned thereby to generate said 01 and 02 pulses respectively at a rate of N pulses/sec. and 180* out-of-phase with one another.