Versatile power converters with a high frequency link

Claim 2

A versatile power converter circuit for converting low frequency and unidirectional electric potentials to desired low frequency and unidirectional output waveforms comprising first and second switching circuits with a single phase high frequency link therebetween connected respectively to a set of first terminals in which appears the electric potential and to a set of second terminals at which the desired output waveform is formed, each switching circuit including a plurality of solid state switching means to establish a plurality of circuit paths through said high frequency link by simultaneous conduction of different combinations of said solid state switching means, and control means for synchronously rendering conductive a selected combination of at least one solid state switching means in each switching circuit for a predetermined interval and for sequentially rendering conductive other selected combinations at a high frequency switching rate to generate a series of energy transfer pulses, wherein said control means includes computing means operative in advance of conduction of an energy transfer pulse for determining and selecting the combination of solid state switching means that produces a minimum error, according to a predetermined criterion, between instantaneous predicted and desired output waveforms.

Claim 3

A circuit according to claim 1 wherein said computing means includes a computation circuit for implementing error equations based on the predetermined criterion and the circuit equations for the predicted output waveform using the different combinations of solid state switching means.

Claim 4

A circuit according to claim 2 wherein said computing means operates during the interval commencing at the start of the previous energy transfer pulse to select the next combination of solid state switching means to be rendered conductive.

Claim 5

A circuit according to claim 2 wherein said control means establishes a turn-off interval between consecutive energy transfer pulses, and said computing means operates during each turn-off interval to select the next combination of said solid state switching means to be rendered conductive.

Claim 6

A circuit according to claim 2 wherein said first and second switching circuits further include series capacitor commutation means comprising commutating inductor means effectively coupled in series circuit relationship with commutating capacitor means and tuned to series resonance at a frequency higher than said switching rate for developing said series of energy transfer pulses, and said computing means operates in the interval created between consecutive energy transfer pulses to select the next combination of solid state switching means to be rendered conductive.

Claim 7

A circuit according to claim 2 wherein the predetermined criterion on which the error equations are based is a least sum of errors squared criterion.

Claim 8

A circuit according to claim 2 wherein the predetermined criterion on which the error equations are based is a least sum of absolute errors criterion.

Claim 9

A circuit according to claim 1 wherein said computing means includes a computation circuit implementing approximate equations for the net effective error, according to the predetermined criterion, for each combination of simultaneously conducting solid state switching means, and a selector circuit for selecting the combination with the minimum net effective error, and a plurality of sensing devices connected in said first and second switching circuits to supply input data to said computation circuit.

Claim 10

A circuit according to claim 8 wherein said computation circuit further computes the net effective error when none of said solid state switching means conducts.

Claim 11

A circuit according to claim 8 wherein said high frequency link comprises a single phase high frequency coupling transformer, and said converter further includes a transformer flux limit circuit for overriding the selection of any combination of solid state switChing means causing saturation of said coupling transformer.

Claim 12

A circuit according to claim 8 wherein said converter further includes a current limit circuit for overriding the selection of any combination of solid state switching means causing the current to exceed a preselected maximum value.

Claim 13

A circuit according to claim 1 wherein said first and second switching circuits are both polyphase circuits, and a plurality of sensing devices connected in said switching circuits to supply input data to said computing means.

Claim 14

A circuit according to claim 1 wherein one of said switching circuits is an inverter circuit and the other switching circuit is a polyphase circuit, and a plurality of sensing devices connected in said switching circuits to supply input data to said computing means.

Claim 15

A circuit according to claim 1 wherein said high frequency link comprises a single phase high frequency linear transformer, and filter capacitor means connected between said first terminals and other filter capacitor means connected between said second terminals.

Claim 16

A circuit according to claim 1 wherein said high frequency link comprises a coupling capacitor, and filter capacitor means connected between said first terminals and other filter capacitor means connected between said second terminals.

Claim 17

A versatile power converter circuit for converting low frequency and unidirectional electric potentials to desired low frequency and unidirectional output waveforms comprising first and second switching circuits with a single phase high frequency link therebetween connected respectively to a set of first terminals in which appears an electric potential and to a set of second terminals at which the desired output waveform is formed, each switching circuit including a plurality of bidirectional conducting solid state switching means to establish a plurality of circuit paths through said high frequency link between said first and second terminals by simultaneous conduction of different combinations of said solid state switching means, and control means including a firing circuit for synchronously rendering conductive a selected combination of at least one solid state switching means in each switching circuit for a predetermined interval and for sequentially rendering conductive other selected combinations at a high frequency switching rate to thereby generate a series of energy transfer pulses, wherein said control means includes a computation circuit operating repetitively in advance of conduction of each energy transfer pulse for computing the net effective error between instantaneous predicted and desired reference output waveforms for each combination of solid state switching means, and a selector circuit for selecting the combination with the minimum net effective error and supplying a signal to said firing circuit.

Claim 18

A versatile power converter circuit for converting low frequency and unidirectional electric potentials to desired low frequency and unidirectional output waveforms comprising first and second switching circuits with a single phase high frequency link therebetween connected respectively to a set of first terminals in which appears an electric potential and to a set of second terminals at which the desired output waveform is formed, each switching circuit including a plurality of bidirectional conducting solid state switching means to establish a plurality of circuit paths through said high frequency link between said first and second terminals by simultaneous conduction of different combinations of said solid state switching means, and control means including a firing circuit for synchronously rendering conductive a selected combination of at least one solid state switching means in each switching circuit for a predetermined interval and for sequentially rendering conductive other selected combinations at a high frequency switching rate to thereby generate a series of energy transfer pulses, wherein said control means includes a computation circuit operating repetitively in advance of conduction of each energy transfer pulse for computing the net effective error between instantaneous predicted and desired reference output waveforms for each combination of solid state switching means, and a selector circuit for selecting the combination with the minimum net effective error and supplying a signal to said firing circuit.

Claim 19

A circuit according to claim 16 wherein a single bidirectional conducting solid state switching means is effectively coupled in series circuit relationship between each terminal of said first and second switching circuits and said high frequency link.

Claim 20

A circuit according to claim 16 wherein at least one of said first and second switching circuit has a plurality of said bidirectional conducting solid state switching means effectively connected in series circuit relationship between each of its respective terminals and said high frequency link to provide additional circuit path options.

Claim 21

A circuit according to claim 16 wherein said high frequency link comprises a single phase high frequency linear transformer, filter capacitor means connected between said first terminals and other filter capacitor means connected between said second terminals, and a plurality of sensing devices connected in said switching circuits to supply input data signals to said net effective error computation circuit.

Claim 22

A circuit according to claim 16 wherein said high frequency link comprises a coupling capacitoR, filter capacitor means connected between said first terminals and other filter capacitor means connected between said second terminals, and a plurality of sensing devices connected in said switching circuits to supply input data signals to said net effective error computation circuit.

Claim 23

A circuit according to claim 16 wherein said first and second switching circuits further include series capacitor commutation means comprising commutating inductor means effectively coupled in series circuit relationship with commutating capacitor means and tuned to series resonance at a frequency higher than said switching rate for developing said series of energy transfer pulses in the form of half sinusoidal current pulses separated by turn-off intervals, and said computation circuit and selector circuit operate in each turn-off interval to select the next combination of solid state switching means with the minimum net effective error.

Claim 24

A circuit according to claim 21 further including lock-out means to inhibit operation of said minimum net effective error selector circuit and firing circuit during conduction of said half sinusoidal current pulses.

Claim 25

A circuit according to claim 22 wherein said computation circuit is arranged to compute the net effective error for each combination of solid state switching means by taking the sum of the squares of the errors between the instantaneous predicted output waveform and the desired reference output waveform.

Claim 26

A circuit according to claim 23 wherein the desired reference output waveform is a voltage waveform having a frequency different from the frequency of the electric potential appearing at said first terminals.

Claim 27

A versatile power converter circuit comprising first and second switching circuits with a single phase high frequency link therebetween connected respectively to a set of first terminals in which appears a low frequency electric potential and to a set of second terminals at which a low frequency output waveform is formed, wherein at least one of said switching circuits is a three-phase circuit, each switching circuit including at least one bidirectional conducting thyristor means effectively connected in series circuit relationship between each of said terminals and said high frequency link to thereby establish a plurality of circuit paths between said first and second terminals by synchronous conduction of different combinations of said thyristor means, said switching circuits further including a series capacitor commutation circuit for said thyristor means that is tuned to series resonance to generate a series of half sinusoidal current pulses as said switching circuits are operated at a high frequency switching rate, a firing circuit for sequentially rendering conductive selected combinations of said thyristor means, and a control computer for controlling said firing circuit including computation circuits for computing the net effective error according to a predetermined criterion between the instantaneous value of a predicted output waveform an a desired reference output waveform for each combination of thyristor means, and a selector circuit for determining the selected combination producing the minimum net effective error, said control computer operating immediately in advance of conduction of each current pulse.

Claim 28

A versatile power converter circuit comprising first and second switching circuits with a single phase high frequency link therebetween connected respectively to a set of first terminals in which appears a low frequency electric potential and to a set of second terminals at which a low frequency output waveform is formed, wherein at least one of said switching circuits is a three-phase circuit, each switching circuit including at least one bidirectional conducting thyristor means effectively connected in series circuit relationship between each of said terminals and said high frequency link to thereby establish a plurality of circuit paths between said first and second terminals by synchronous conduction of different combinations of said thyristor means, said switching circuits further including a series capacitor commutation circuit for said thyristor means that is tuned to series resonance to generate a series of half sinusoidal current pulses as said switching circuits are operated at a high frequency switching rate, a firing circuit for sequentially rendering conductive selected combinations of said thyristor means, and a control computer for controlling said firing circuit including computation circuits for computing the net effective error according to a predetermined criterion between the instantaneous value of a predicted output waveform an a desired reference output waveform for each combination of thyristor means, and a selector circuit for determining the selected combination producing the minimum net effective error, said control computer operating immediately in advance of conduction of each current pulse.

Claim 29

A circuit according to claim 25 wherein both of said switching circuits are three-phase circuits, and said desired reference output waveform has a frequency different from that of the electric potential appearing at said first terminals.

Claim 30

A circuit according to claim 25 wherein one of said switching circuits is a single phase inverter.

Claim 31

A circuit according to claim 25 wherein at least one of said switching circuits has a pair of bidirectional conducting thyristor means connected effectively in parallel circuit relationship between each respective terminal and said high frequency link to provide dual circuit paths and increase thE number of different combinations.

Claim 32

A circuit according to claim 25 wherein said high frequency link comprises a coupling capacitor, and said coupling capacitor has the dual function of being the commutating capacitor of said series capacitor commutation circuit.

Claim 35

A method according to claim 30 including the steps of supplying to said control computer a reference output waveform corresponding to the desired output waveform to be formed at said second terminals, and sensing and supplying to said control computer predetermined electrical signals indicative of the state of said first and second switching circuits.

Claim 36

A method according to claim 30 including the step of providing a turn-off interval between consecutive energy transfer pulses, and performing the steps of computing the net effective error for each combination and selecting the next combination with the minimum net effective error during each turn-off interval.

Claim 37

A method according to claim 32 including the additional step of effectively sensing the cessation of each energy transfer pulse, and delaying the timing of the turn-off interval until each energy transfer pulse has ceased.

Claim 38

A method according to claim 30 including the step of computing also the net effective error when none of said solid state switching means is rendered conductive.

Claim 39

A method according to claim 30 including the step of changing said reference output waveform between consecutive energy transfer pulses to obtain an adjustable output waveform at said second terminals.

Claim 40

A method according to claim 30, wherein said power converter high frequency link comprises a coupling transformer, including the steps of computing the predicted transformer flux for each combination of said solid state switching means, and overriding the selection of any combination that causes saturation of the transformer flux.

Claim 41

A method according to claim 30 including the steps of computing the predicted current for each combination of said solid state switching means, and overriding the selection of any combination for which the predicted current rises above a predetermined maximum value.