Method and apparatus for etching fine line patterns in metal on semiconductive devices

Claim 2

The method of claim 2 wherein the framing aperture pattern in the insulative layer is an intersecting grid pattern.

Claim 3

The method of claim 1 wherein the step of etching the exposed portion of the metal layer includes the step of, electrolytic etching the exposed portions of the metal layer in an electrolytic cell.

Claim 4

The method of claim 1 wherein the step of etching the metal layer includes the step of anodizing the exposed portions of the metal layer.

Claim 5

In a method for making semiconductive devices the steps of, forming first and second subregions of differing conductivity type in a semiconductive substrate, forming first and second fine line pattern apertures in an electrically insulative layer overlaying the substrate with the first and second fine line patterns of apertures disposed in registration over the first and second subregions, respectively, depositing a metal layer over the apertured insulative layer for making electrical contact to the respective first and second subregions, forming first, second and third patterns of etch-resistant material over the metal film, each of said first and second patterns of etch-resistant material having a fine line portion overlaying the respective first and second subregions and an enlarged electrical pad portion overlaying the insulative layer, the layer of etch-resistant material having an apertured pattern opening to expose the metal layer, such opening pattern in the etch-resistant layer having a fine line pattern portion disposed in between the fine line portions of the first and second patterns of etch-resistant material and a field portion overlaying the insulative layer in the regions surrounding the pad portions of the first and second patterns of etch-resistant material and a third pattern of etch-resistant material being formed over the metal layer bridging a region thereof between the field portion of the aperture pattern in the etch-resistant material and un underlying contactor aperture in the insulative layer to the semiconductive substrate, such contactor aperture being covered by the metal layer, and etching the metal film through the aperture pattern in the etch-resistant material to form first, second and third metal electrode patterns on the semiconductive device, such first and second electrode patterns having fine line portions and the third electrode pattern forming an electrical conductor providing an electrically conductive path between the field region of the device and the semiconductive substrate such electrical conductive path being separate from other conductive paths from the field to the substrate through the first and second electrodes.

Claim 6

The method of claim 6 wherein the aperture in the insulative layer through which the third electrode pattern makes electrical contact between the field region of the metal layer and the semiconductive substrate is an aperture which surrounds the first and second electrode patterns.

Claim 7

The method of claim 7 wherein there are a multitude of first and second electrode pairs formed on the semi-conductive substrate, and wherein the aperture which surrounds the first and second electrode patterns has a pattern of intersecting grid lines defining an aperture pattern which frames each of the electrode pairs.

Claim 8

The method of claim 8 wherein the third electrodes are formed at intersecting corners of the framing aperture pattern.

Claim 9

The method of claim 6 wherein the step of etching the exposed portions of the metal layer includes the step of, electrolytic etching the exposed portions of the metal layer in an electrolytic cell.

Claim 10

The method of claim 6 wherein the step of etching the exposed portions of the metal layer includes the step of anodizing the exposed portions of the metal layer.

Claim 11

In a semiconductive device, a semiconductive substrate member having a first regiOn of a first conductivity type, a second region of said substrate member having a second conductivity type forming a P-N junction at the interface of the first and second regions of said substrate, said second region of said substrate having a fine line pattern portion forming a fine line P-N junction pattern at the interface with said first region of said substrate, a layer of electrically insulative material disposed overlaying said substrate, said insulative layer having apertures in a pattern in registration over said second region of said substrate and forming a fine line aperture pattern portion of said insulative layer, a first metallic layer electrode overlaying portions of said insulative layer including portion of the apertured pattern in registration with said second region in the fine line portion of said substrate and providing an electrode path for electrical connection to said first region of said substrate through said second region of said substrate, an electrical lead affixed to said first metallic electrode, and a second metallic layer electrode having a first portion disposed over said insulative layer and having a second portion extending over the outer edge of said insulative layer to said substrate and forming an electrically conductive path therebetween.