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US3678301A Expired / Lapsed US ⏱️ 0.0 years remaining

Logic module connected to act as flipflop

Assignee: Licentia Patent Verwaltungs GmbH
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Filing: 1971-02-19
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Granted: 1972-07-18
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Expires: 1991-02-19
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Abstract

Abstract A flipflop circuit having a first pair of transistors having their bases connected to receive input signals and their collectors arranged to produce output signals, the transistors assuming respectively opposite switching states depending on the relative levels of the inputs thereto, a conductor connecting the collector of one transistor to one of the inputs of the other transistor for causing the transistors to remain in their existing switching states after the removal of input signals, and a second pair of transistors each having its base connected to the base of a respective transistor of the first pair and providing at their collectors the direct and complement output signals for the circuit. Means are provided to selectively place a conductive path across the emitter-collector of one transistor of the first pair, thereby to suppress the storage capability of the circuit.

Inventors

  • 👤 Gerd Fischer
  • 👤 Dieter Straub
  • 👤 Heinz Eberhard Voigt

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 19:54
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/027; H03K3/037; H03K5/00

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 296 words
In a logic circuit composed of a first pair of transistors whose emitters are coupled together and are connected to one terminal of a current supply course, the transistors assuming respectively opposite switching states which depend on the relative levels of the control signals applied to their bases, a first pair of collector load resistors each connected to the collector of a respective transistor, at least one emitter follower stage for each transistor having its output connected to the base of its respective transistor and having an input for receiving an input signal, a direct voltage source connected to one transistor of said first pair and poled for reducing the control voltage to its transistor, and conductor means connected between the collector of the other transistor and the input of one emitter follower stage for the one transistor for applying the output of said other transistor to control the one transistor so as to store the output signal being produced by the circuit beyond the period of effectiveness of the input signals, the improvement comprising: a further pair of transistors having their emitters coupled together and connected to one terminal of a further current supply source and each having its base conductively connected to the base of a respective transistor of said first pair; and a further pair of collector load resistors each connected to the collector of a respective transistor of said further pair; said transistors of said further pair assuming respectively opposite switching states which depend on the relative levels of the signals applied to their bases, the resulting output signal of said circuit appearing at the collector of one transistor of said further pair and the complement of such output signal appearing at the collector of the other transistor of said further pair.
Claim 2
Dependent Claim 296 words
In a logic circuit composed of a first pair of transistors whose emitters are coupled together and are connected to one terminal of a current supply course, the transistors assuming respectively opposite switching states which depend on the relative levels of the control signals applied to their bases, a first pair of collector load resistors each connected to the collector of a respective transistor, at least one emitter follower stage for each transistor having its output connected to the base of its respective transistor and having an input for receiving an input signal, a direct voltage source connected to one transistor of said first pair and poled for reducing the control voltage to its transistor, and conductor means connected between the collector of the other transistor and the input of one emitter follower stage for the one transistor for applying the output of said other transistor to control the one transistor so as to store the output signal being produced by the circuit beyond the period of effectiveness of the input signals, the improvement comprising: a further pair of transistors having their emitters coupled together and connected to one terminal of a further current supply source and each having its base conductively connected to the base of a respective transistor of said first pair; and a further pair of collector load resistors each connected to the collector of a respective transistor of said further pair; said transistors of said further pair assuming respectively opposite switching states which depend on the relative levels of the signals applied to their bases, the resulting output signal of said circuit appearing at the collector of one transistor of said further pair and the complement of such output signal appearing at the collector of the other transistor of said further pair.
Claim 3
Dependent Claim 51 words
An arrangement as defined in claim 1 further comprising an additional transistor having its collector-emitter path connected in parallel with the collector-emitter path of the other transistor of said first pair, and means for selectively placing said additional transistor in a conductive state for suppressing the storage capability of said circuit.
Claim 4
Dependent Claim 63 words
An arrangement as defined in claim 2 wherein said means for placing comprise an additional emitter follower stage having its output connected to the base of said additional transistor and arranged to control said additional transistor in response to a control signal having the same amplitude level as the input signals applied to said at least one emitter follower stage for each transistor.

References Cited (Backward Citations)

US3339089A Cited
US3548221A Cited
US3573488A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-07-18 1976-01-17 1976-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-07-18 1980-01-17 1980-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-07-18 1984-01-17 1984-07-18 $7700.00 Window Closed / Lapsed

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