Patent US5762625A successfully refreshed from Google Patents.
US3673503A
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Harmonic suppression circuit
Assignee: General Electric Co
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Filing: 1971-07-06
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Granted: 1972-06-27
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Expires: 1991-07-06
Abstract
Abstract A harmonic suppression circuit in which the fundamental component of the test voltage is blocked out by means of a phase inverting, frequency selective amplifier while the harmonic component of the test voltage is fed back out of phase with the normally generated harmonic component of the test voltage.
Inventors
- 👤 Harold F Parker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:24
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/04; H03H11/12; H03H11/1217; H03H11/1252; G; G01; G01R; G01R1/00; G01R1/30
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
148 words
A harmonic suppression circuit for use in test apparatus wherein harmonics are generated by a material under test as a fundamental frequency is applied to the input of said apparatus to develop an output signal, said circuit comprising: circuit means for coupling said output signal to a first path and a second path, said first path and said second path having a common input and a common output; circuit means in said second path for substantially reducing said harmonic frequencies, and amplifying and reversing the phase of said fundamental frequency in said second path; circuit means for recombining said signals from said first and said second path at said common output to provide a residue signal comprising substantially said harmonic frequencies of said output signal; and circuit means for combining said residue signal with said fundamental frequency of said output signal at the input of said test apparatus.
Claim 2
Dependent Claim
148 words
A harmonic suppression circuit for use in test apparatus wherein harmonics are generated by a material under test as a fundamental frequency is applied to the input of said apparatus to develop an output signal, said circuit comprising: circuit means for coupling said output signal to a first path and a second path, said first path and said second path having a common input and a common output; circuit means in said second path for substantially reducing said harmonic frequencies, and amplifying and reversing the phase of said fundamental frequency in said second path; circuit means for recombining said signals from said first and said second path at said common output to provide a residue signal comprising substantially said harmonic frequencies of said output signal; and circuit means for combining said residue signal with said fundamental frequency of said output signal at the input of said test apparatus.
Claim 3
Dependent Claim
51 words
A circuit as in claim 1 wherein said circuit means for reducing said harmonic frequencies and amplifying and reversing the phase of said fundamental frequency in said second path comprises an attenuator and a frequency selective amplifier, the output of said attenuator connected to the input of said frequency selective amplifier.
Claim 4
Dependent Claim
12 words
A circuit as in claim 2 wherein said attenuator includes a potentiometer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-27 | 1975-12-27 | 1976-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-27 | 1979-12-27 | 1980-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-27 | 1983-12-27 | 1984-06-27 | $7700.00 | Window Closed / Lapsed |