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US3673433A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit arrangement for selectively connecting at least two inputs to a counting stage possessing at least one preparatory input and one triggering input and including contact bounce suppression circuitry

Assignee: Siemens Schweiz AG
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Filing: 1971-07-26
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Granted: 1972-06-27
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Expires: 1991-07-26
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Abstract

Abstract A circuit arrangement for selectively connecting at least two inputs to a counting stage equipped with at least one preparatory input and one triggering input, wherein these inputs are connected in circuit with the triggering input of the counting stage through the agency of associated gates and a successively arranged common gate. A respective input of each associated gate is connected to a voltage via a respective switch controlling such gate. For the purpose of slowing down or retarding the switching-in signal flank there is connected in series with each switch an inductance coil and a damping resistor which collectively form in conjunction with a respective grounded capacitor an at least approximately critically damped series oscillating circuit. The junction point between each damping resistor and associated capacitor is connected via a diode and a common resistor to an oppositely poled voltage, and the junction point between each such diode and the common resistor is connected with the preparatory input of the counting stage.

Inventors

  • 👤 Hanspeter Kupfer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 07:21
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/02; H03K3/00; H03K3/01; H03K3/013

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 201 words
A circuit arrangement for selectively connecting at least two inputs to a counting stage equipped with at least one preparatory input and one triggering input, comprising a respective gate in electrical circuit association with each input, a common gate in circuit with and following said gates associated with the inputs, said inputs being connected via said associated gates and said common gate with said triggering input of the counting stage, each said associated gate having an input means, each input means of each associated gate being connected to a first voltage via a respective switch controlling such associated gate, an inductance coil and a damping resistor connected in series with each said switch for retarding the switching-in flank, a respective grounded capacitor in circuit with each series connected inductance coil and damping resistor and forming together with such an at least approximately critically damped series oscillating circuit, a common resistor for said series oscillating circuits, a respective diode for connecting the junction point of each damping resistor and associated capacitor with an oppositely poled voltage via said common resistor, and means for connecting the junction point between each diode and said common resistor with the preparatory input of the counting stage.
Claim 2
Dependent Claim 201 words
A circuit arrangement for selectively connecting at least two inputs to a counting stage equipped with at least one preparatory input and one triggering input, comprising a respective gate in electrical circuit association with each input, a common gate in circuit with and following said gates associated with the inputs, said inputs being connected via said associated gates and said common gate with said triggering input of the counting stage, each said associated gate having an input means, each input means of each associated gate being connected to a first voltage via a respective switch controlling such associated gate, an inductance coil and a damping resistor connected in series with each said switch for retarding the switching-in flank, a respective grounded capacitor in circuit with each series connected inductance coil and damping resistor and forming together with such an at least approximately critically damped series oscillating circuit, a common resistor for said series oscillating circuits, a respective diode for connecting the junction point of each damping resistor and associated capacitor with an oppositely poled voltage via said common resistor, and means for connecting the junction point between each diode and said common resistor with the preparatory input of the counting stage.
Claim 3
Dependent Claim 237 words
A circuit arrangement for selectively connecting at least two inputs to a counting stage equipped with at least one preparatory input and one triggering input, comprising a respective gate in electrical circuit association with each input, each gate having an output, a common gate electrically coupled with the outputs of said gates associated with the inputs, said inputs being connected via said associated gates and said common gate with said triggering input of the counting stage, a first voltage, each said associated gate having an input means, a respective switch controlling each of said associated gates, each input means of each associated gate being connected via its switch with said first voltage, an inductance coil and a damping resistor connected in series with each switch for retarding the switching-in signal flank, a grounded capacitor provided for each series connected inductance coil and damping resistor, each said grounded capacitor and series connected inductance coil and damping resistor collectivelY forming an at least approximately critically damped series oscillating circuit, a common resistor for all of said series oscillating circuits, a second voltage oppositely poled with respect to said first voltage, a respective diode for connecting the junction point of each damping resistor and its associated capacitor with said oppositely poled second voltage via said common resistor, and means for connecting the junction point between each said diode and said common resistor with the preparatory input of the counting stage.
Claim 4
Dependent Claim 237 words
A circuit arrangement for selectively connecting at least two inputs to a counting stage equipped with at least one preparatory input and one triggering input, comprising a respective gate in electrical circuit association with each input, each gate having an output, a common gate electrically coupled with the outputs of said gates associated with the inputs, said inputs being connected via said associated gates and said common gate with said triggering input of the counting stage, a first voltage, each said associated gate having an input means, a respective switch controlling each of said associated gates, each input means of each associated gate being connected via its switch with said first voltage, an inductance coil and a damping resistor connected in series with each switch for retarding the switching-in signal flank, a grounded capacitor provided for each series connected inductance coil and damping resistor, each said grounded capacitor and series connected inductance coil and damping resistor collectivelY forming an at least approximately critically damped series oscillating circuit, a common resistor for all of said series oscillating circuits, a second voltage oppositely poled with respect to said first voltage, a respective diode for connecting the junction point of each damping resistor and its associated capacitor with said oppositely poled second voltage via said common resistor, and means for connecting the junction point between each said diode and said common resistor with the preparatory input of the counting stage.

References Cited (Backward Citations)

US2723346A Cited
US3333111A Cited
DE1290587B Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-06-27 1975-12-27 1976-06-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-06-27 1979-12-27 1980-06-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-06-27 1983-12-27 1984-06-27 $7700.00 Window Closed / Lapsed

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