US3673343A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Anti-jamming circuit for multi-frequency signal detector
Assignee: Individual
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Filing: 1968-11-21
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Granted: 1972-06-27
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Expires: 1988-11-21
Abstract
Abstract A jam-proof circuit for use with a multi-frequency signal detector system to prevent noise from erroneously actuating the detector system. The circuit employs substantially similar high and low-band exclusive OR circuits interposed between the output of the multi-frequency signal detector means and associated logic circuitry. The exclusive OR circuitry prevents noise from causing erroneous indications to be produced by the logic circuitry which comprises an individual AND gate corresponding to each digit that may be signalled. The digits are identified by the simultaneous transmission of a plurality of different frequencies.
Inventors
- 👤 Robert E Vosteen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:33
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/453
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
230 words
A jam-proof decoder circuit to prevent noise from causing false indications for detecting signals at a number of different predetermined frequencies in low and high band frequency ranges comprising: a plurality of first input sources corresponding in number to that of the different predetermined frequencies in the high band frequency range, a plurality of second input sources corresponding in number to that of the different predetermined frequencies in the low band frequency range, a high band digital exclusive OR circuit having a first amplifier, the plurality of first input sources being connected to a first common input terminal of the first amplifier, a low band digital exclusive OR circuit having a second amplifier, the plurality of second input sources being connected to a second common input terminal of the second amplifier, bias means connected to the first and second common input terminals to control the first and second amplifiers to assume output states corresponding to the signals applied to the first and second input sources respectively, logic means including a matrix array having a first group of lines individually connected to different ones of the first and second input sources and a second group of lines connected to the outputs of the high and low band exclusive OR circuits and including gating means to provide an indication of true signals at the predetermined frequencies which are present in the circuit.
Claim 2
Dependent Claim
230 words
A jam-proof decoder circuit to prevent noise from causing false indications for detecting signals at a number of different predetermined frequencies in low and high band frequency ranges comprising: a plurality of first input sources corresponding in number to that of the different predetermined frequencies in the high band frequency range, a plurality of second input sources corresponding in number to that of the different predetermined frequencies in the low band frequency range, a high band digital exclusive OR circuit having a first amplifier, the plurality of first input sources being connected to a first common input terminal of the first amplifier, a low band digital exclusive OR circuit having a second amplifier, the plurality of second input sources being connected to a second common input terminal of the second amplifier, bias means connected to the first and second common input terminals to control the first and second amplifiers to assume output states corresponding to the signals applied to the first and second input sources respectively, logic means including a matrix array having a first group of lines individually connected to different ones of the first and second input sources and a second group of lines connected to the outputs of the high and low band exclusive OR circuits and including gating means to provide an indication of true signals at the predetermined frequencies which are present in the circuit.
Claim 3
Dependent Claim
71 words
A jam-proof decoder circuit as recited in claim 1 wherein the first and second amplifiers assume first output states when only one signal at one of the associated predetermined frequencies is applied to one of the plurality of first and second inputs, respectively, and second output states when no signal or more than one signal at the associated predetermined frequencies are applied to the plurality of first and second inputs, respectively.
Claim 4
Dependent Claim
24 words
A jam-proof decoder circuit as recited in claim 1 wherein the first and second amplifiers comprise operational amplifiers functioning as multiple input summing amplifiers.
Claim 5
Dependent Claim
48 words
A jam-proof decoder circuit as recited in claim 1 further comprising: limiter means connected between the output and input of each of the first and second amplifiers to limit the outputs thereof in the event more than two signals at the predetermined frequencies are applied to their inputs.
Claim 6
Dependent Claim
78 words
A jam-proof decoder circuit as recited in claim 1 wherein the first and second amplifiers each comprise: first and second operational amplifiers, the plurality of respective inputs being connected to the input of the first operational amplifier, delay means connected to the outputs of the first and second operational amplifiers to prevent erroneous indications during the initial transient response of the system, the delay means of the first and second amplifier means being connected to the logic means.
Claim 7
Dependent Claim
31 words
A jam-proof decoder circuit as recited in claim 5 wherein first and second amplifiers are interposed between the outputs of each first and second operational amplifier, respectively, and the delay means.
Claim 8
Dependent Claim
42 words
A jam-proof decoder circuit as recited in claim 6 wherein each of the second operational amplifiers connected to function as a unity gain inverter providing an output that is an inverted replica of the output of the respectively connected first operational amplifier.
Claim 9
Dependent Claim
136 words
An exclusive OR circuit comprising: a plurality of inputs corresponding in number to that of different predetermined frequencies that may be applied thereto, the plurality of inputs being connected to a common input terminal of a first amplifier, bias means connected to the common input terminal of the first amplifier to control the latter to assume output states corresponding to the signals applied to the plurality of inputs, a second amplifier connected at its input to the output of the first amplifier, delay means connected to the outputs of the first and second amplifiers to prevent erroneous circuit output signals during the initial transient response of the circuit to input signals thereto, indicating means connected to the delay means responsive to provide an indication of signals at the predetermined frequencies that are present in the circuit.
Claim 10
Dependent Claim
136 words
An exclusive OR circuit comprising: a plurality of inputs corresponding in number to that of different predetermined frequencies that may be applied thereto, the plurality of inputs being connected to a common input terminal of a first amplifier, bias means connected to the common input terminal of the first amplifier to control the latter to assume output states corresponding to the signals applied to the plurality of inputs, a second amplifier connected at its input to the output of the first amplifier, delay means connected to the outputs of the first and second amplifiers to prevent erroneous circuit output signals during the initial transient response of the circuit to input signals thereto, indicating means connected to the delay means responsive to provide an indication of signals at the predetermined frequencies that are present in the circuit.
Claim 11
Dependent Claim
30 words
An exclusive OR circuit as recited in claim 8 wherein first and second rectifiers are interposed between the outputs of the first and second amplifiers, respectively, and the delay means.
Claim 12
Dependent Claim
33 words
An exclusive OR circuit as recited in claim 9 wherein the second amplifier comprises a unity gain inverter providing an output that is an inverted replica of the output of the first amplifier.
Claim 13
Dependent Claim
18 words
An exclusive OR circuit as recited in claim 10 wherein the first and second amplifiers comprise operational amplifiers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-27 | 1975-12-27 | 1976-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-27 | 1979-12-27 | 1980-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-27 | 1983-12-27 | 1984-06-27 | $7700.00 | Window Closed / Lapsed |