US3671939A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Per-cycle basis frequency signal receiver
Assignee: AT&T Inc
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Filing: 1970-10-15
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Granted: 1972-06-20
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Expires: 1990-10-15
Abstract
Abstract In a communication system, signal tones are detected with protection against the false recognition of spurious tones by an arrangement that includes the combination of a per-cycle switch and a time delay circuit. Presence of signal tone continuously throughout each cycle or group of cycles is required rather than the conventional test for an ''''on-the-average'''' presence of tone throughout a given period.
Inventors
- 👤 David Carlaw Trimble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:14
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/446; H04Q1/4465
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
164 words
A signal receiver for producing an output signal in response to a valid oscillatory input signal comprising, in combination, a limiter circuit, a bandpass amplifier, a threshold detector, a time delay circuit and an output circuit connected in tandem relation, said time delay circuit including means responsive to an output signal from said threshold detector exceeding a preselected threshold for a preselected substantially continuous duration, said last named means including means responsive only to said last named signals present for substantially each signal cycle occuring during said substantially continuous duraTion, said means responsive to an output signal comprising a timing capacitor and means for charging said capacitor linearly with time in response to said last named signal and means for discharging said capacitor at a rate substantially greater than the charging rate thereof in response to a break in said last named signal, thereby precluding the building up of a charge on said capacitor in response to a succession of short spurious input signals.
Claim 2
Dependent Claim
164 words
A signal receiver for producing an output signal in response to a valid oscillatory input signal comprising, in combination, a limiter circuit, a bandpass amplifier, a threshold detector, a time delay circuit and an output circuit connected in tandem relation, said time delay circuit including means responsive to an output signal from said threshold detector exceeding a preselected threshold for a preselected substantially continuous duration, said last named means including means responsive only to said last named signals present for substantially each signal cycle occuring during said substantially continuous duraTion, said means responsive to an output signal comprising a timing capacitor and means for charging said capacitor linearly with time in response to said last named signal and means for discharging said capacitor at a rate substantially greater than the charging rate thereof in response to a break in said last named signal, thereby precluding the building up of a charge on said capacitor in response to a succession of short spurious input signals.
Claim 3
Dependent Claim
120 words
In a single frequency signal receiver, a time delay circuit for ensuring signal validity by requiring an input signal of continuous duration throughout each signal cycle over a preselected period, said circuit comprising a per-cycle switch responsive to the output from a threshold detector, a first current source controlled by said switch, a timing capacitor, a second current source, a level detector, means connecting one side of said timing capacitor to said level detector, a feedback path connecting said level detector to said second current source, whereby said second current source produces an output only when said capacitor is charged above the threshold of said level detector, and means for applying the difference between said current sources to said capacitor.
Claim 4
Dependent Claim
120 words
In a single frequency signal receiver, a time delay circuit for ensuring signal validity by requiring an input signal of continuous duration throughout each signal cycle over a preselected period, said circuit comprising a per-cycle switch responsive to the output from a threshold detector, a first current source controlled by said switch, a timing capacitor, a second current source, a level detector, means connecting one side of said timing capacitor to said level detector, a feedback path connecting said level detector to said second current source, whereby said second current source produces an output only when said capacitor is charged above the threshold of said level detector, and means for applying the difference between said current sources to said capacitor.
Claim 5
Dependent Claim
15 words
Apparatus in accordance with claim 2 wherein said capacitor is shunted by rapid discharge means.
Claim 6
Dependent Claim
62 words
Apparatus in accordance with claim 3 wherein said rapid discharge means comprises the collector-emitter path of a transistor, said last named transistor operating as a current sink to provide a low impedance rapid discharge path for said capacitor under conditions when said capacitor is not being charged and when the voltage of said capacitor is below the threshold of said level detector.
Claim 7
Dependent Claim
103 words
In a single frequency signal receiver, a time delay circuit for ensuring signal validity by requiring input signal duration throughout each signal cycle over a preselected period, said circuit comprising a per-cycle transistor switch responsive to the output from a threshold detector, a level detector circuit, a timing capacitor having one terminal thereof connected to the input of said level detector circuit, a first current source controlled by said switch, a second current source controlled by a feedback path from the output of said level detector, and means for applying the difference between said first and second current sources to charge said capacitor.
Claim 8
Dependent Claim
103 words
In a single frequency signal receiver, a time delay circuit for ensuring signal validity by requiring input signal duration throughout each signal cycle over a preselected period, said circuit comprising a per-cycle transistor switch responsive to the output from a threshold detector, a level detector circuit, a timing capacitor having one terminal thereof connected to the input of said level detector circuit, a first current source controlled by said switch, a second current source controlled by a feedback path from the output of said level detector, and means for applying the difference between said first and second current sources to charge said capacitor.
Claim 9
Dependent Claim
33 words
Apparatus in accordance with claim 5 including means responsive to preselected conditions for discharging said capacitor at a rate that exceeds the net charging rate thereof by at least an order of magnitude.
Claim 10
Dependent Claim
22 words
Apparatus in accordance with claim 6 wherein said discharging means comprises a transistor having the emitter-collector path thereof connected across said capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-20 | 1975-12-20 | 1976-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-20 | 1979-12-20 | 1980-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-20 | 1983-12-20 | 1984-06-20 | $7700.00 | Window Closed / Lapsed |