US3671783A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample and hold circuit
Assignee: United States Department of the Air Force
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Filing: 1971-06-15
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Granted: 1972-06-20
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Expires: 1991-06-15
Abstract
Abstract A balanced sample and hold circuit in which a pair of transistors control the bias on a pair of diodes and these transistors are activated by pulses applied to the bases thereof. The diodes connect the input signals to the output terminals and there is a holding capacitor in shunt with the output terminals. Resistors are connected across the input terminal to provide a load when the circuit is in the off condition.
Inventors
- 👤 Daniel Hampel
- 👤 Joseph Bryan Lerch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:18
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
144 words
A sample and hold circuit comprising: a. a pair of input terminals; b. a pair of output terminals; c. a pair of diodes, each having an anode and a cathode with the anode of each diode connected to one each of the input terminals and the cathode of each diode connected one each to the output terminals; d. a pair of transistors, each having a base, emitter, and collector with the collector of each transistor connected to one each of the cathodes of each diode; e. a control terminal connected to each base of the transistors; f. a capacitor connected in shunt with the output terminals; g. a source of bias potential; and h. a first pair of series resistors connected in parallel with the capacitor, the mutual junction of the first pair of series resistors being connected to the source of bias potential.
Claim 2
Dependent Claim
144 words
A sample and hold circuit comprising: a. a pair of input terminals; b. a pair of output terminals; c. a pair of diodes, each having an anode and a cathode with the anode of each diode connected to one each of the input terminals and the cathode of each diode connected one each to the output terminals; d. a pair of transistors, each having a base, emitter, and collector with the collector of each transistor connected to one each of the cathodes of each diode; e. a control terminal connected to each base of the transistors; f. a capacitor connected in shunt with the output terminals; g. a source of bias potential; and h. a first pair of series resistors connected in parallel with the capacitor, the mutual junction of the first pair of series resistors being connected to the source of bias potential.
Claim 3
Dependent Claim
35 words
A sample and hold circuit according to claim 1 which further comprises a second pair of series resistors connected to the input terminals, with the mutual junction of the second pair of resistors being grounded.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-20 | 1975-12-20 | 1976-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-20 | 1979-12-20 | 1980-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-20 | 1983-12-20 | 1984-06-20 | $7700.00 | Window Closed / Lapsed |