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US3671770A Expired / Lapsed US ⏱️ 0.0 years remaining

Temperature compensated bias circuit

Assignee: Motorola Solutions Inc
•
Filing: 1970-08-17
•
Granted: 1972-06-20
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Expires: 1990-08-17
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Abstract

Abstract Disclosed is a monolithic voltage regulator having a high current capability, a constant low output impedance from DC to several hundred kilocycles, and a high ripple reduction factor. The regulator has excellent transient response; it provides a wide range of regulated output voltage and has a low temperature drift. The voltage regulator includes a voltage standard or bias source, an input differential amplifier stage having a pair of transistors coupled to a current sink (a current source passing current to ground), and one of the transistors in the pair is connected through a current gain stage to an output terminal. A DC reference shifting circuit is connected to the input of one transistor in the pair and provides a reference voltage to the differential amplifier stage which has been translated to provide the required voltage level at the output terminal. The output terminal is connected directly to the input of the other transistor in the pair in order to achieve a unity feed back factor to provide excellent constant loop performance independent of the output voltage. The direct coupled feedback connection eliminates any undesirable gain loss and phase shifting due to resistance in the input circuits of the differentially coupled transistor pair.

Inventors

  • 👤 Thomas M Frederiksen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 18:28
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/575

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 166 words
A temperature-independent bias stage for producing a standard voltage, having an input terminal and an output terminal, comprising: a Zener diode; constant current means for causing a constant current to flow through the Zener diode to a first terminal so that a constant voltage is produced across the Zener diode; a reference transistor, having two main electrodes oppositely positioned between the input terminal and the output terminal, and having a control electrode; at least one other diode connected between the output terminal and the first terminal; two of said semi-conducting elements having opposite temperature coefficients, and means for connecting the contrOl electrode between the constant current means and the Zener diode so that the constant voltage appears across the control electrode and the other diode, causing a constant current to flow through the two main electrodes of the reference transistor and the other diode to the first terminal, to produce a reference voltage between the output terminal and the first terminal for application to a load.
Claim 2
Dependent Claim 166 words
A temperature-independent bias stage for producing a standard voltage, having an input terminal and an output terminal, comprising: a Zener diode; constant current means for causing a constant current to flow through the Zener diode to a first terminal so that a constant voltage is produced across the Zener diode; a reference transistor, having two main electrodes oppositely positioned between the input terminal and the output terminal, and having a control electrode; at least one other diode connected between the output terminal and the first terminal; two of said semi-conducting elements having opposite temperature coefficients, and means for connecting the contrOl electrode between the constant current means and the Zener diode so that the constant voltage appears across the control electrode and the other diode, causing a constant current to flow through the two main electrodes of the reference transistor and the other diode to the first terminal, to produce a reference voltage between the output terminal and the first terminal for application to a load.
Claim 3
Dependent Claim 82 words
The invention of claim 1 in which the constant current means comprises a PNP and an NPN transistor each having an emitter, a collector and a base, a connection to a source terminal by way of respective resistors to the emitter of said PNP transistor and to the base of said NPN transistor, and a connection between the emitter of said NPN transistor to the base of said PNP transistor, said collector of said PNP transistor being connected to said Zener diode.
Claim 4
Dependent Claim 21 words
The invention of claim 1 in which said diode comprises an NPN transistor having its base short circuited to its collector.
Claim 5
Dependent Claim 39 words
The invention of claim 3 in which a resistor is connected between a main electrode of the reference transistor and said other diode and the output terminal is connected to a point between said resistor and the reference transistor.
Claim 6
Dependent Claim 99 words
The invention of claim 4 in which a fourth and a fifth transistor each having main electrodes and a control electrode are provided, the output terminal being connected to the control electrode of said fourth transistor, and a main electrode of said fourth transistor being connected to the control electrode of said fifth transistor and the emitter of said NPN transistor being connected by way of the main electrode of said fifth transistor to the first terminal, whereby said fourth transistor acts to prevent said fifth transistor from loading the circuit between the reference transistor and said first terminal.
Claim 7
Dependent Claim 62 words
The invention of claim 5 in which said Zener diode has positive temperature coefficient voltage produced thereacross, said first resistor has positive temperature coefficient of resistance, the reference transistor and said other diode have negative coefficient of voltage drop from the base to the emitters thereof, whereby the variation in the voltage applied to said load with variations in temperature is reduced.

References Cited (Backward Citations)

US3271660A Cited
US3262062A Cited
US3566293A Cited
US3436672A Cited
US3518458A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-06-20 1975-12-20 1976-06-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-06-20 1979-12-20 1980-06-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-06-20 1983-12-20 1984-06-20 $7700.00 Window Closed / Lapsed

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