US3668657A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automation control system
Assignee: Individual
•
Filing: 1969-11-21
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Granted: 1972-06-06
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Expires: 1989-11-21
Abstract
Abstract A pulse sampling multiplex system with analog capabilities including a modulating means necessary for direct recording on magnetic tape, an analog DC output, a direct DC output, an AC power output and a servomotor control output, a means for revising information on any channel without altering data on other channels, a ''''memory'''' means whereby information can be retained in the system after input data has been discontinued and a means for controlling direct DC and AC power output by punched tape or other parallel digital input means.
Inventors
- 👤 Edwin R Deloach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:57
CPC Classifications
G; G08; G08C; G08C15/00; G08C15/06; G08C15/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
295 words
A signal multiplex coding-decoding system comprising: a coding circuit including a clock circuit and a binary counting circuit of two or more stages, said clock circuit generating timing pulses applied to said binary counting circuit; said binary counting circuit''s second and succeeding stages generating a binary output which is fed to a multiple number of commutator circuits; said commutator circuits comprising an AND gate and field effect transistor; said commutator commutating during a time interval enabled by a single binary code as determined by said code connected to said AND gate of said commutator; a signal generated by said commutating circuit being applied to a modulating circuit; said binary counting circuit first stage providing a signal applied to said modulating circuit; said modulating circuit alternately gating the signal generated by said commutator circuit; the signal derived from said binary counting circuit first stage providing the signal to operate the gates of said modulating circuit whereby the output of said modulating circuit is inverted in polarity of voltage through one of the gates of said modulating circuit; and a decoding circuit comprising the identical circuits of the coding section and additionally comprising: an input circuit which feeds the input signal to a clock synchronizing circuit; said clock synchronizing circuit providing a signal generating from said input circuit and applying this signal to said clock circuit whereby said clock circuit frequency is thus synchronized with said input signal; a second signal provided from said input circuit to a frame synchronizing circuit whereby said frame synchronizing Circuit is generating a signal which sets said binary counting circuits to a count corresponding to a reference pulse channel position; said input circuit applying the input signal to the output of said modulator circuit whereby demodulation occurs, providing a demodulated output.
Claim 2
Dependent Claim
295 words
A signal multiplex coding-decoding system comprising: a coding circuit including a clock circuit and a binary counting circuit of two or more stages, said clock circuit generating timing pulses applied to said binary counting circuit; said binary counting circuit''s second and succeeding stages generating a binary output which is fed to a multiple number of commutator circuits; said commutator circuits comprising an AND gate and field effect transistor; said commutator commutating during a time interval enabled by a single binary code as determined by said code connected to said AND gate of said commutator; a signal generated by said commutating circuit being applied to a modulating circuit; said binary counting circuit first stage providing a signal applied to said modulating circuit; said modulating circuit alternately gating the signal generated by said commutator circuit; the signal derived from said binary counting circuit first stage providing the signal to operate the gates of said modulating circuit whereby the output of said modulating circuit is inverted in polarity of voltage through one of the gates of said modulating circuit; and a decoding circuit comprising the identical circuits of the coding section and additionally comprising: an input circuit which feeds the input signal to a clock synchronizing circuit; said clock synchronizing circuit providing a signal generating from said input circuit and applying this signal to said clock circuit whereby said clock circuit frequency is thus synchronized with said input signal; a second signal provided from said input circuit to a frame synchronizing circuit whereby said frame synchronizing Circuit is generating a signal which sets said binary counting circuits to a count corresponding to a reference pulse channel position; said input circuit applying the input signal to the output of said modulator circuit whereby demodulation occurs, providing a demodulated output.
Claim 3
Dependent Claim
170 words
The apparatus of claim 1 wherein said clock circuit includes a unijunction transistor; the emitter of said unijunction transistor connecting to the cathode of a rectifier diode; the anode of said rectifier diode connecting to a time constant circuit comprising a resistor and capacitor; said resistor connecting to a source of voltage; said capacitor connecting to a ground reference point; said capacitor discharging through said diode; and said emitter and base of said unijunction transistor, a signal is being generated and providing the clock output; said frame synchronizing circuit comprising one or more amplifier stages biased into cutoff; the output of the final stage of said amplifier stages being connected to the base of a frame synchronizing circuit unijunction transistor which in turn is connected to said time constant of the clock circuit through a frame synchronizing circuits rectifier diode; whereby a signal on said amplifier stages triggers said frame synchronizing circuit into conduction, discharging the stored charge on said time constant circuit capacitor providing an output for frame synchronization.
Claim 4
Dependent Claim
136 words
The apparatus of claim 1 wherein said clock synchronizing circuit comprises: two transistors, first transistor emitter connecting to a second transistor emitter, base of said first transistor connected to the ends of a transformer winding, said second transistor connecting to the opposite end of said transformer winding a center top of said transformer winding connecting to a variable voltage supply, collectors of said first transistor connecting to a first rectifier diode, collector of said second transistor connecting to a second rectifier diode, said first rectifier diode anode terminal connecting to second rectifier anode terminal, said anode terminals connecting to the cathode of a third rectifier diode, said third rectifier diode connecting to a grand reference point, junction of all three of said rectifier diodes connected to resistance, and said resistance connecting to a source of voltage.
Claim 5
Dependent Claim
99 words
The apparatus of claim 1 wherein said modulator circuit comprises two field effect transistors, said transistor source terminals connected in common to a signal line, said transistor drain terminals connected to opposite ends of a transformer winding having a center top of said transformer winding connected to a ground reference point and the gates of said field effect transistors connected to individual terminal points where application of a modulating signal is applied and whereby a signal can be applied into a secondary winding of the transformer and extracted at the common connection of said source terminals or vice versa.
Claim 6
Dependent Claim
67 words
The apparatus of claim 1 wherein said commutator circuit comprises a resistor array of which all connections are common on one end and connects to the gate terminal of a field effect transistor of which the source terminal of said field effect transistor connects to a point common with all commutator circuits and where the drain terminal of said field effect transistor connecting to a terminal point.
Claim 7
Dependent Claim
80 words
The circuit of claim 5 wherein a second field effect transistor is connected so that the gate of said second field effect transistor is connected to the gate of said field effect transistor of claim 5; the drain of said second field effect transistor is connected to the drain of said field effect transistor of claim 5; the source terminal of said second field effect transistor connection common to all other second field effect transistors of all other commutator circuits.
Claim 8
Dependent Claim
142 words
The circuit of claim 5 wherein said drain terminal connects to a direct current control circuit which consists of:a capacitor connected from said drain terminal to a grounD reference point; a resistor which connects said drain terminal with the gate terminal of a SCR transistor ; where said SCR anode terminal connects to a load that is connected to a source of interrupting direct durrents; a resistor connecting to said SCR cathode and the other end of said resistor connecting to a ground reference point; a second resistor connecting to said SCR cathode and the other end of said second resistor connecting to said drain terminal so application of a signal of the drain terminal turns said SCR transistor into conduction; whereby once conducting will restore energy taken from said capacitor which connects from said drain terminal to a ground reference point.
Claim 9
Dependent Claim
54 words
The circuit of claim 7 wherein the cathode of said SCR is connected to the gate of a TRIAC transistor whereby when said SCR transistor is conduction a signal is applied switching said TRIAC transistor on energizing a load whereby said load connected from said TRIAC transistors anode to a source of AC power.
Claim 10
Dependent Claim
144 words
The apparatus of claim 1 where said commutating circuit comprises a first diode array on which all connections are common on one end and connects to the gate terminal of a field effect transistor and a second diode array of opposite polarity commonly connected at one end connects to its gate terminal of a second field effect transistor of opposite polarity; the drain terminals of said first transistors connected to the source terminal of the second; drain terminal of said first transistor connects to a terminal point where a signal can be applied during decommutation; the source terminal of the second transistor connects to a terminal point; whereby each diode of said first diode array connects to terminals of which is applied a control signal and where each diode of said second diode array connects to terminals of which is applied a control signal.
References Cited (Backward Citations)
US2787418A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |