US3668638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pattern processing systems
Assignee: Toshiba Corp
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Filing: 1970-11-02
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Granted: 1972-06-06
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Expires: 1990-11-02
Abstract
Abstract Each input pattern supplied for the purpose of identification is translated through light energy into an electrical signal which is then quantized and stored in a two-dimensional register. The quantized values in the register, consisting of binary digits 0 (representing a white spot) and 1 (a black spot), may be further subjected to a process of a blurring operation and/or that of line width normalization. The pattern blurring operation is effected by means of sampling circuits with their resistances preadjusted at specific values. The latter process is carried out by means of a line width normalization circuit capable of detecting the line width of sampled pattern obtained by the above sampling procedure and of feeding back the results of the detection of the two-dimensional register or the quantizing circuit for the readjustment, if necessary, of the line width into a desired range.
Inventors
- 👤 Taizo Iijima
- 👤 Issei Yamazaki
- 👤 Shunji Mori
- 👤 Hiroshi Genchi
- 👤 Sumio Katsuragi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:53
CPC Classifications
G; G06; G06V; G06V10/00; G06V10/20; G06V10/34; G06V10/36
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
96 words
A pattern processing system comprising sampling means including weighting/summing means for sampling a twodimensionally represented pattern to produce sampled pattern signals corresponding to a sampled and blurred representation of said two-dimensional pattern, identifying means having said sampled pattern signals applied thereto for identifying said pattern by comparison with a plurality of predetermined patterns, detecting means having said sample pattern signals applied thereto for detecting the line widths of said two-dimensional pattern, and means connecting said detecting means to said sampling means for normalizing the line widths of said sampled and blurred representation of said two-dimensional pattern.
Claim 2
Dependent Claim
96 words
A pattern processing system comprising sampling means including weighting/summing means for sampling a twodimensionally represented pattern to produce sampled pattern signals corresponding to a sampled and blurred representation of said two-dimensional pattern, identifying means having said sampled pattern signals applied thereto for identifying said pattern by comparison with a plurality of predetermined patterns, detecting means having said sample pattern signals applied thereto for detecting the line widths of said two-dimensional pattern, and means connecting said detecting means to said sampling means for normalizing the line widths of said sampled and blurred representation of said two-dimensional pattern.
Claim 3
Dependent Claim
73 words
A pattern processing system as set forth in claim 1, in which said sampling means includes means for sampling said two-dimensional pattern at sampling points spaced to satisfy the equation: 0 < or = a < or = 0.637 Square Root sigma o2 + (( b/1.4))2, where 2a the width between sampling points of the pattern; 2b the line width of said pattern; and, sigma o the standard deviation of the desired blurring.
Claim 4
Dependent Claim
78 words
A pattern processing system as set forth in claim 1, in which said sampling means comprises a plurality of summing amplifiers, each said summing amplifier including: an operational amplifier having an output terminal, and having a plurality of input terminals connected in common; a plurality of resistors respectively connected to said plurality of inputs; and, a feedback resistor connected at one end to said output terminal, and connected at its other end to said commonly connected input terminals.
Claim 5
Dependent Claim
55 words
A pattern processing system as set forth in claim 1, in which said weighting summing means comprises a plurality of digital adder circuits each having an input terminal for receiving a sample signal, and means connected to said digital adder circuit input terminals for weighting said sample signals according to the desired degree of blurring.
Claim 6
Dependent Claim
84 words
A pattern processing system comprising sampling means for producing electrical signals corresponding to a two-dimensional sample pattern, identifying means connected to said sampling means for identifying said sample pattern in response to said electrical signals, detecting means connected to said sampling means for detecting the line width of the sample pattern in response to said electrical signals, and means coupled between said sampling means and said detecting means for controlling said electrical signals to normalize a pattern line width represented by said electrical signals.
Claim 7
Dependent Claim
84 words
A pattern processing system comprising sampling means for producing electrical signals corresponding to a two-dimensional sample pattern, identifying means connected to said sampling means for identifying said sample pattern in response to said electrical signals, detecting means connected to said sampling means for detecting the line width of the sample pattern in response to said electrical signals, and means coupled between said sampling means and said detecting means for controlling said electrical signals to normalize a pattern line width represented by said electrical signals.
Claim 8
Dependent Claim
164 words
A pattern processing system comprising a source of input electrical signals representing a two-dimensional input pattern, quantizing circuit means having an input connected to said source, and having an output for producing quantized signals representing said input pattern in response to said input signals, two-dimensional register means having a plurality of outputs, and having an input connected to said quantizing means output for temporarily storing said quantized signals, sampling circuit means connected to said register means for sampling said quantized signals at said respective register means outputs, said sampling circuit means including weighting/summing means for processing said sampled quantized signals, identifying means connected to said weighting/summing means for identifying said input pattern, and line width normalization circuit means having an input connected to said weighting/summing means for detecting a difference between a sampled line width and a reference line width, and having an output connected to said quantizing circuit means and said two-dimensional register means for controlling said quantized signals representing said input pattern.
Claim 9
Dependent Claim
164 words
A pattern processing system comprising a source of input electrical signals representing a two-dimensional input pattern, quantizing circuit means having an input connected to said source, and having an output for producing quantized signals representing said input pattern in response to said input signals, two-dimensional register means having a plurality of outputs, and having an input connected to said quantizing means output for temporarily storing said quantized signals, sampling circuit means connected to said register means for sampling said quantized signals at said respective register means outputs, said sampling circuit means including weighting/summing means for processing said sampled quantized signals, identifying means connected to said weighting/summing means for identifying said input pattern, and line width normalization circuit means having an input connected to said weighting/summing means for detecting a difference between a sampled line width and a reference line width, and having an output connected to said quantizing circuit means and said two-dimensional register means for controlling said quantized signals representing said input pattern.
Claim 10
Dependent Claim
95 words
A pattern processing system as claimed in claim 6, in which said line width normalization circuit comprises a plurality of maximum value detecting circuits each capable of detecting a maximum value possessed by the outputs supplied from each of equally divided groups of said sampling circuits, a minimum value detecting circuit for detecting the smallest of the maximum values detected by said plurality of maximum value detecting circuits, and a level detector which transmits a line width normalizing signal when the output of said minimum value detecting circuit supplied thereto is off a predetermined level.
Claim 11
Dependent Claim
31 words
A pattern processing system as claimed in claim 7, in which said line width normalization circuit has a feedback path to said quantizing circuit thereby to control the quantization level thereof.
Claim 12
Dependent Claim
43 words
A pattern processing system as claimed in claim 7, in which said line width normalization circuit has a feedback path to said two-dimensional register thereby to logically control the line width of the input pattern as represented by said quantized values stored therein.
References Cited (Backward Citations)
US3341814A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |