US3668429A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier latch for monolithic memories
Assignee: International Business Machines Corp
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Filing: 1970-09-22
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Granted: 1972-06-06
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Expires: 1990-09-22
Abstract
Abstract A sense amplifier latching circuit for accepting signals from a monolithic memory array. The input signal from the monolithic memory is amplified, the logical sense of the input is determined and held in the latch, and the signal is translated down to current switch logic circuit levels having a capability for large fan-out and fan-in (dot or). The input to the sense amplifier latch has a grounded base clamp providing a very low impedance input in the presence of bi-polar noise current. The sense amplifier latch circuit further includes threshold tracking, temperature compensating, and power supply compensating circuits. The entire circuit includes emitter follower and grounded base circuits providing a high band width resulting in fast rise-time and low propagation delay.
Inventors
- 👤 Richard A Ainsworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/067; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C7/065
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
187 words
A sense amplifier latching circuit for accepting data signals from a monolithic memory array comprising: an input node; an output node; input means having a low impedance and connected to said input node, said input means being biased to a threshold current level; differential circuit means connected to the output of said input means; latching means connected to the output of said differential circuit means for providing an output at said output node and holding the signal at said output node at a set level regardless of subsequent variations in the signal at the input node; a source of power connected to said latching means, such that fluctuations in the potential of said power source tend to cause corresponding fluctuations in the potential level of the output; and a current source connected between the input node and the said same power supply, said current source adjusting the threshold current at the input node thereby varying the output of said differential circuit means, compensating for fluctuations in said power supply and maintaining the potential at the output node at a constant level in the presence of such fluctuations.
Claim 2
Dependent Claim
187 words
A sense amplifier latching circuit for accepting data signals from a monolithic memory array comprising: an input node; an output node; input means having a low impedance and connected to said input node, said input means being biased to a threshold current level; differential circuit means connected to the output of said input means; latching means connected to the output of said differential circuit means for providing an output at said output node and holding the signal at said output node at a set level regardless of subsequent variations in the signal at the input node; a source of power connected to said latching means, such that fluctuations in the potential of said power source tend to cause corresponding fluctuations in the potential level of the output; and a current source connected between the input node and the said same power supply, said current source adjusting the threshold current at the input node thereby varying the output of said differential circuit means, compensating for fluctuations in said power supply and maintaining the potential at the output node at a constant level in the presence of such fluctuations.
Claim 3
Dependent Claim
17 words
A circuit as in claim 1 wherein said power supply compensating means is a variable current source.
Claim 4
Dependent Claim
54 words
A circuit as in claim 1 wherein said current source comprises: a transistor having collector, base and emitter regions, the collector being connected to the input node, the base being connected to an impedance in said input means; and a resistor connected between the emitter of said transistor and the said same power supply.
Claim 5
Dependent Claim
163 words
In a sense amplifier latching circuit for accepting data signals from a monolithic memory array, and having a low impedance input means biased to a threshold current level, the means for biasing including a pair of resistors with significantly different resistance values, said data signals from said monolithic memory array changing with variations in the power supply of said monolithic memory array, the improvement comprising: a current source connected to said input means for providing greater variation in the threshold current level in response to a given fluctuation in the monolithic memory array power supply, thereby minimizing the effect of input signal variations caused by fluctuations in the power supply of the monolithic memory array; said current source being a transistor including collector, base and emitter region and having its collector region connected to the input node, its base region connected to an impedance means; and impedance means connected to the emitter of said transistor and also connected to a source of potential.
Claim 6
Dependent Claim
163 words
In a sense amplifier latching circuit for accepting data signals from a monolithic memory array, and having a low impedance input means biased to a threshold current level, the means for biasing including a pair of resistors with significantly different resistance values, said data signals from said monolithic memory array changing with variations in the power supply of said monolithic memory array, the improvement comprising: a current source connected to said input means for providing greater variation in the threshold current level in response to a given fluctuation in the monolithic memory array power supply, thereby minimizing the effect of input signal variations caused by fluctuations in the power supply of the monolithic memory array; said current source being a transistor including collector, base and emitter region and having its collector region connected to the input node, its base region connected to an impedance means; and impedance means connected to the emitter of said transistor and also connected to a source of potential.
References Cited (Backward Citations)
US3452223A
Cited
US3588535A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |