Arrangement for controlling devices transmitting digital pulses in a computer controlled telecommunication system

Claim 1

An arrangement in a computer controlled telecommunication system for transmitting pulse trains of required numbers of digit pulses from address-defined output devices comprising a first register means for receiving a number associated with the number of digit pulses to be transmitted in a pulse train, second register means for receiving the address of the output device to transmit said pulse train, a scanning means having a first plurality of scan outputs which are Sequentially energized and a second plurality of scan outputs which are sequentially energized, a first comparator means having a first input connected to the output of said first register means, a second input, and an output which is activated when number-representing signals at the inputs thereof have a particular relationship, at least one buffer unit, said buffer unit comprising a pulse generating means for generating digit pulses, a plurality of memory cells for storing addresses of said output devices, first logic means for connecting said memory cells and said pulse generating means to said output devices for permitting the passage of digit pulses to particular output devices in accordance with addresses stored in said memory cells, a pulse counting means stepped to an end position by pulses from said pulse generating means, said pulse counting means including endposition indicating means, the count stored in said pulse counting means defining the number of pulses to be generated by said pulse generating means, and position indicating means connected to said pulse counting means, means connected to the particular first scan output associated with said one buffer unit and to said end-position indicating means for presetting said pulse counting means to the number stored in said first register means and for transferring the address stored in said second register means to one of said memory cells, means connected to the particular second scan output associated with said one buffer unit and to said pulse counting means for transferring the number stored in said pulse counting means to the second input of said first comparator means for comparison with the number stored in said first register means, and means operative when the output of said first comparator means is activated for transferring the address in said second register means to an empty memory cell whereby the output device defined by the address stored in said memory cell transmits a number of digit pulses indicated by the count in said pulse counting means which is equal to the number stored in said first register means.