US3668329A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiregister for time-division switching network
Assignee: Individual
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Filing: 1970-03-31
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Granted: 1972-06-06
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Expires: 1990-03-31
Abstract
Abstract Multiregister for automatic telephone time-division switching networks having a circulating store for subscriber data in the form of series recorder words, constructions for modifying the breaking or making of subscribers+ circuits, booking access circuit and rebooking circuit for entering modified data, three read-out circuits in the store, and first, second and third series-parallel converters connected to the read-out circuits, whereby a directive address in the circulating store from the first series to parallel converter goes to a processing unit in the second and third series to parallel converter and is modified by the modifying data to permit the modified data to be collected and processed in parallel from the read-out circuits while this modifying data advances into the circulating store, the data after modification being entered in series.
Inventors
- 👤 Daniel G Hardy
- 👤 Daniel E Goby
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:20
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
357 words
In a pulse code modulated time-division telephone switching system having subscriber lines connected thereto and including means for testing said subscriber lines: a switching processor comprising a circulating store in which series register words circulate in cycles; said register words containing data relating to the addresses of the subscriber lines which are to be connected with each other, directive address data relating to the addresses of the directives of a program of connection and disconnection of subscriber lines and directive address change control data for controlling the changes of said program directive address data; said directive address change control data originating from said testing means; a plurality of read-out circuits inserted along said circulating store where the subscriber line address data, the program directive address data and the directive address change control data are read-out, respectively, at sequential times; a write-in circuit inserted in said circulating store; series-to-parallel converters respectively connected to said read-out circuits; a parallel-to-series converter connected to said write-in circuit; a directive address register operated by the directive address data contained in the register word and a directive store associated thereto; a parallel operated computer means for computing the data relating to the address of a new directive from the directive address change control data contained in a register word and from a directive originating from said directive store; said computer means comprising a plurality of computer stages having inputs and outputs and operated at sequential times respectively coinciding with the read-out sequential times; said directive address register and computer stage inputs being respectively connected to said read-out circuits through said series-to-parallel converters and said computer means output being connected to said write-in circuit through said parallelto-series converter whereby, at the successive sequential times, the directive register receives directive address data from the first read-out circuit, the first stage of the computer means receives a directive from the directive store and the directive address change control data from the second read-out circuit, and each other stage of the computer means receives partially processed data from the preceding stage and also from the directive address change control data of the third and following read-out circuits.
Claim 2
Dependent Claim
357 words
In a pulse code modulated time-division telephone switching system having subscriber lines connected thereto and including means for testing said subscriber lines: a switching processor comprising a circulating store in which series register words circulate in cycles; said register words containing data relating to the addresses of the subscriber lines which are to be connected with each other, directive address data relating to the addresses of the directives of a program of connection and disconnection of subscriber lines and directive address change control data for controlling the changes of said program directive address data; said directive address change control data originating from said testing means; a plurality of read-out circuits inserted along said circulating store where the subscriber line address data, the program directive address data and the directive address change control data are read-out, respectively, at sequential times; a write-in circuit inserted in said circulating store; series-to-parallel converters respectively connected to said read-out circuits; a parallel-to-series converter connected to said write-in circuit; a directive address register operated by the directive address data contained in the register word and a directive store associated thereto; a parallel operated computer means for computing the data relating to the address of a new directive from the directive address change control data contained in a register word and from a directive originating from said directive store; said computer means comprising a plurality of computer stages having inputs and outputs and operated at sequential times respectively coinciding with the read-out sequential times; said directive address register and computer stage inputs being respectively connected to said read-out circuits through said series-to-parallel converters and said computer means output being connected to said write-in circuit through said parallelto-series converter whereby, at the successive sequential times, the directive register receives directive address data from the first read-out circuit, the first stage of the computer means receives a directive from the directive store and the directive address change control data from the second read-out circuit, and each other stage of the computer means receives partially processed data from the preceding stage and also from the directive address change control data of the third and following read-out circuits.
Claim 3
Dependent Claim
388 words
In a pulse code modulated time-division telephone switching system having subscriber lines connected thereto: a switching processor comprising a circulating store in which series register words circulate in cycles; said register words containing data relating to the addresses of the subscriber lines which are to be connected with each other, directive address data relating to the addresses of the directives of a program Of connection and disconnection of subscriber lines, and directive address change control data for controlling the changes of said program directive address data; a plurality of read-out circuits inserted along said circulating store where the subscriber line address data, the program directive address data and the directive address change control data are read-out, respectively, at sequential times; a write-in circuit inserted in said circulating store; series-to-parallel converters respectively connected to said read-out circuits; a parallel-to-series converter connected to said write-in circuit; a detector of the loop states of the subscriber lines and a store means for storing data representing said loop states and forming part of said directive address change control data; a directive address register operated by the directive data contained in the register word and a directive store associated thereto; a parallel operated computer means for computing the data relating to the address of a new directive from the directive address change control data contained in a register word and from a directive originating from said directive store; said computer means comprising a plurality of computer stages having inputs and outputs and operated at sequential times respectively coinciding with the read-out sequential times; said loop state detector, directive address register and computer stage inputs being respectively connected to said read-out circuits through said series-to-parallel converters and said loop state store means and said computer means output being connected to said write-in circuit through said parallel-to-series converter whereby, at the successive sequential times, the loop state detector and the directive register respectively receive subscriber line address data and directive address data from the first read-out circuit, the first stage of the computer means receives a directive from the directive store and the directive address change control data from the second read-out circuit, and each other stage of the computer means receives partially processed data from the preceding stage and also from the directive address change control data of the third and following read-out circuits.
Claim 4
Dependent Claim
388 words
In a pulse code modulated time-division telephone switching system having subscriber lines connected thereto: a switching processor comprising a circulating store in which series register words circulate in cycles; said register words containing data relating to the addresses of the subscriber lines which are to be connected with each other, directive address data relating to the addresses of the directives of a program Of connection and disconnection of subscriber lines, and directive address change control data for controlling the changes of said program directive address data; a plurality of read-out circuits inserted along said circulating store where the subscriber line address data, the program directive address data and the directive address change control data are read-out, respectively, at sequential times; a write-in circuit inserted in said circulating store; series-to-parallel converters respectively connected to said read-out circuits; a parallel-to-series converter connected to said write-in circuit; a detector of the loop states of the subscriber lines and a store means for storing data representing said loop states and forming part of said directive address change control data; a directive address register operated by the directive data contained in the register word and a directive store associated thereto; a parallel operated computer means for computing the data relating to the address of a new directive from the directive address change control data contained in a register word and from a directive originating from said directive store; said computer means comprising a plurality of computer stages having inputs and outputs and operated at sequential times respectively coinciding with the read-out sequential times; said loop state detector, directive address register and computer stage inputs being respectively connected to said read-out circuits through said series-to-parallel converters and said loop state store means and said computer means output being connected to said write-in circuit through said parallel-to-series converter whereby, at the successive sequential times, the loop state detector and the directive register respectively receive subscriber line address data and directive address data from the first read-out circuit, the first stage of the computer means receives a directive from the directive store and the directive address change control data from the second read-out circuit, and each other stage of the computer means receives partially processed data from the preceding stage and also from the directive address change control data of the third and following read-out circuits.
References Cited (Backward Citations)
US3524946A
Cited
US3404237A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |