Sample, hold, and subtract circuit

Claim 3

A method according to claim 1 in which the step of obtaining a baseline signal comprises the steps of: repetitively sampling said baseline potential when no circuit input signal is present; deriving a baseline signal by multiplying the baseline potential by a factor for each sample, whereby said baseline signal represents said baseline potential; successively storing the derived baseline signal for each sample; and stopping the repetitive sampling as soon as a circuit input signal appears, whereby the last baseline signal stored represents the baseline potential occurring immediately before the circuit input signal.

Claim 4

A method according to claim 2 in which the step operating on the circuit input signal comprises the steps of: obtaining a further circuit input signal representing the circuit input signal by multiplying the circuit input signal by a factor; and subtracting the baseline signal from the further circuit input signal to obtain an output signal representing the circuit input signal corrected for baseline drift.

Claim 5

In a baseline correction circuit for removing a baseline potential from circuit input signals that occur repetitively with the baseline, the baseline correction circuit having a clock pulse source and identification means for providing a first identification signal indicating the presence of said circuit input signal and a second identification signal indicating the presence of only said baseline potential, a sample, hold and subtract circuit, comprising: storage means for storing a baseline signal representing said baseline potential; and sampling means for applying the baseline signal to the storage means each time both a clock signal and said second identification signal are provided and for inhibiting the application of the baseline signal to the storage means when said first identification signal is provided, whereby said baseline signal is stored during the clock pulse occuring immediately before said first identification signal; said sampling means including subtracting means for operating on the circuit input signal and the baseline signal stored immediately before the first identification signal to provide a difference signal representing the difference between said combined circuit input signal and the baseline signal and said baseline potential during said first identification signal.

Claim 6

In a baseline correction circuit for removing a baseline potential from circuit input signals that occur repetitively with the baseline, the baseline correction circuit having a clock pulse source and identification means for providing a first identification signal indicating the presence of said circuit input signal and a second identification signal indicating the presence of only said baseline potential, a sample, hold and subtract circuit, comprising: storage means for storing a baseline signal representing said baseline potential; and sampling means for applying the baseline signal to the storage means each time both a clock signal and said second identification signal are provided and for inhibiting the application of the baseline signal to the storage means when said first identification signal is provided, whereby said baseline signal is stored during the clock pulse occuring immediately before said first identification signal; said sampling means including subtracting means for operating on the circuit input signal and the baseline signal stored immediately before the first identification signal to provide a difference signal representing the difference between said combined circuit input signal and the baseline signal and said baseline potential during said first identification signal.

Claim 7

A sample, hold, and subtract circuit according to claim 4 in which said sampling means comprises gate means, electrically connected to said clock pulse source and said identification means, for connecting said baseline potential to said storage means upon concurrently receiving a clock pulse and said second identification signal.

Claim 8

A sample, hold, and subtract circuit according to claim 5 in which: said gate means comprises a gate having first and second inputs and one output and a switch electrically connected to the output of said gate; said first input being electrically connected to said source of clock pulses and said second input being electrically connected to said identification means; said storage means including a capacitor.

Claim 9

A sample, hold, and subtract circuit according to claim 4 in which said sampling means comprises operator means for multiplying said baseline potential by a factor to derive said baseline signal, for holding said baseline signal on said storage means, for multiplying said circuit input signal by said factor to obtain a further circuit input signal, and for subtracting said baseline signal from said further circuit input signal.

Claim 10

A sample, hold, and subtract circuit according to claim 7 in which said operator means comprises: an operational amplifier; a first impedance having one end electrically connected to the output of said operational amplifier and having the other end electrically connected to one end of said storage means, the other end of said storage means being electrically connected to the input Of said operational amplifier; a second impedance having one end electrically connected to said first impedance and having its other end electrically connected to receive said circuit input signals; said operational amplifier having a high input impedance, whereby said baseline signal is held on said storage means.

Claim 11

A sample, hold, and subtract circuit having a circuit input terminal for receiving circuit input signals and a circuit output terminal for providing a circuit output signal that is a function of the circuit input signal at a first time subtracted from the circuit input signal at a second time, comprising: a first impedance having a first impedance first end and a first impedance second end; said first impedance first end being electrically connected to said circuit input terminal; a second impedance having a second impedance first end and a second impedance second end; said second impedance second end being electrically connected to said circuit output terminal; storage means, having a first storage terminal electrically connected to said second impedance first end and having a second storage terminal, for storing a function of said circuit input signal at said first time; said first impedance second end being electrically connected to said second impedance; and operator means, electrically connecting said second impedance second end and said second storage terminal, for holding the potential at said second storage terminal and second impedance second end at a reference potential during said first time, whereby a function of said circuit input signal is impressed on said storage means, and for holding the potential at said second storage terminal at said reference potential while permitting the potential at said second impedance second end to fluctuate at said second time, whereby said circuit output terminal receives an output signal that is said function of the circuit input signal at said first time subtracted from the circuit input signal at said second time.

Claim 12

A sample, hold, and subtract circuit having a circuit input terminal for receiving circuit input signals and a circuit output terminal for providing a circuit output signal that is a function of the circuit input signal at a first time subtracted from the circuit input signal at a second time, comprising: a first impedance having a first impedance first end and a first impedance second end; said first impedance first end being electrically connected to said circuit input terminal; a second impedance having a second impedance first end and a second impedance second end; said second impedance second end being electrically connected to said circuit output terminal; storage means, having a first storage terminal electrically connected to said second impedance first end and having a second storage terminal, for storing a function of said circuit input signal at said first time; said first impedance second end being electrically connected to said second impedance; and operator means, electrically connecting said second impedance second end and said second storage terminal, for holding the potential at said second storage terminal and second impedance second end at a reference potential during said first time, whereby a function of said circuit input signal is impressed on said storage means, and for holding the potential at said second storage terminal at said reference potential while permitting the potential at said second impedance second end to fluctuate at said second time, whereby said circuit output terminal receives an output signal that is said function of the circuit input signal at said first time subtracted from the circuit input signal at said second time.

Claim 13

A sample, hold, and subtract circuit according to claim 9 in which said operator means includes a means for holding the potential at said second storage terminal at said reference potential while permitting the potential at said second impedance second end to fluctuate between said first time and said second time, whereby said function of said circuit input signal at said first time is stored on said storage means at least between said first time and second time.

Claim 14

A sample, hold, and subtract circuit according to claim 9 in which said operator means includes an operational amplifier having an operational amplifier input terminal electrically connected to said second storage terminal and an operational amplifier output terminal electrically connected to said second second end; said storage means comprising a capacitor and said first and second impedances comprising resistors.