Electrical inverter circuit arrangements

Claim 2

An electrical inverter circuit arrangement, comprising a plurality of transistors, control means connected to the transistors and operative when energized to cause the transistors to be switched on and off in a predetermined order and including, for each transistor, a control circuit operative in response to a TURN ON Pulse to switch the transistor on and in response to a TURN OFF pulse to switch the transistor off, each control circuit including a switching device blocking the application of a turn on current to the transistor until rendered operative, time delay means responsive to each TURN ON pulse to render the device operative after a time delay whereby to feed turn on current to the transistor to switch it on, and means responsive to each TURN OFF pulse to bypass the switching device whereby each TURN OFF pulse immediately feeds turn off current to the transistor to switch it off, the length of the said time delay being such as to delay the switching on of each of the transistors sufficiently to ensure that the preceding transistor in the said order is first switched off.

Claim 3

An electrical inverter circuit arrangement, comprising a plurality of transistors, control means connected to the transistors and operative when energized to cause the transistors to be switched on and off in a predetermined order and including a respective control circuit connected to each transistor and operative in response to a TURN ON pulse to switch the transistor on and in response to a TURN OFF pulse to switch the transistor off, each said control circuit comprising an electronic switching device connected in circuit with the respective transistor to block each TURN ON pulse applied to the control circuit until the switching device is rendered operative, a time delay circuit connected to the switching device and responsive to each TURN ON pulse applied to the circuit to render the switching device operative after a time delay so that the TURN ON pulse is then applied to the respective transistor and switches it on, and unidirectional conducting means connected to provide a path by passing the switching device which path immediately feeds each TURN OFF pulse applied to the control circuit to the respective transistor to switch it off, the length of the said time delay being such as to delay the switching on of each of the transistors sufficiently to ensure that the preceding transistor in the said order is first switched off.

Claim 4

An electrical inverter circuit arrangement, comprising a plurality of transistors, control means connected to the transistors and operative when energized to cause the transistors to be switched on and off in a predetermined order and including a respective control circuit connected to each transistor and operative in response to a TURN ON pulse to switch the transistor on and in response to a TURN OFF pulse to switch the transistor off, each said control circuit comprising an electronic switching device connected in circuit with the respective transistor to block each TURN ON pulse applied to the control circuit until the switching device is rendered operative, a time delay circuit connected to the switching device and responsive to each TURN ON pulse applied to the circuit to render the switching device operative after a time delay so that the TURN ON pulse is then applied to the respective transistor and switches it on, and unidirectional conducting means connected to provide a path by passing the switching device which path immediately feeds each TURN OFF pulse applied to the control circuit to the respective transistor to switch it off, the length of the said time delay being such as to delay the switching on of each of the transistors sufficiently to ensure that the preceding transistor in the said order is first switched off.

Claim 5

A circuit arrangement according to claim 2, in which each electronic switching device comprises a controlled rectifier device having cathode, anode and gate electrodes and connected in the base-emitter circuit of the respective transistor whereby to block the application of the TURN ON pulse to the base and emitter of the transistor until the device is rendered conductive, and each time delay circuit comprises a resistance-capacitance circuit connected to respond to the TURN ON pulse and having the gate electrode of the respective one of the controlled rectifier devices connected to it whereby that controlled rectifier device is rendered conductive after the said time delay.

Claim 6

A circuit arrangement according to claim 3, in which each control circuit has a pair of terminals for receipt of the TURN ON and TURN OFF pulses, one terminal being connected to the base of the respective transistor, the other connected to the emitter thereof through the controlled rectifier device, and in which the resistance-capacitance time delay circuit is connected across the two terminals with the gate and cathode electrodes of the controlled rectifier device connected across the capacitance thereof.

Claim 7

An electrical inverter circuit arrangement, comprising at least two transistors, means connecting their emitter-collector paths in parallel, a respective control circuit associated with each transistor for turning it on and off, means applying TURN ON and TURN OFF pulses respectively and simultaneously to the two control circuits whereby to switch one transistor on and the other off, and output means responsive to the current in at least one of the said paths whereby to produce an alternating output when the transistors are rendered conductive alternately, each control circuit comprising a respective electronic switching device connected in the base-emitter circuit of the transistor so as to allow a turn-on current to pass through the transistor in response to each said TURN ON pulse only when the electronic switching device is rendered conductive, a time delay circuit responsive to each said TURN ON pulse and connected to the electronic switching device whereby to render the electronic switching device conductive after a predetermined time delay so as to feed the said turn on current to the transistor, and unidirectional conducting means connected in parallel with the electronic switching device and so poled as to allow turn off current to flow through the transistor in response to each TURN OFF pulse applied to the control circuit, whereby the TURN ON and TURN OFF pulses respectively and simultaneously applied to the two control circuits switch one transistor off and, after the said predetermined time delay, switch the other transistor on, the predetermined time delay being of length such that the one transistor is completely switched off before the other is switched on.

Claim 8

An electrical inverter circuit arrangement, comprising at least two transistors, means connecting their emitter-collector paths in parallel, a respective control circuit associated with each transistor for turning it on and off, means applying TURN ON and TURN OFF pulses respectively and simultaneously to the two control circuits whereby to switch one transistor on and the other off, and output means responsive to the current in at least one of the said paths whereby to produce an alternating output when the transistors are rendered conductive alternately, each control circuit comprising a respective electronic switching device connected in the base-emitter circuit of the transistor so as to allow a turn-on current to pass through the transistor in response to each said TURN ON pulse only when the electronic switching device is rendered conductive, a time delay circuit responsive to each said TURN ON pulse and connected to the electronic switching device whereby to render the electronic switching device conductive after a predetermined time delay so as to feed the said turn on current to the transistor, and unidirectional conducting means connected in parallel with the electronic switching device and so poled as to allow turn off current to flow through the transistor in response to each TURN OFF pulse applied to the control circuit, whereby the TURN ON and TURN OFF pulses respectively and simultaneously applied to the two control circuits switch one transistor off and, after the said predetermined time delay, switch the other transistor on, the predetermined time delay being of length such that the one transistor is completely switched off before the other is switched on.

Claim 9

A circuit arrangement according to claim 3, in which each electronic switching device is a semi-conductor controlled rectifier device, and each time delay circuit is a resistance-capacitance circuit.

Claim 10

A circuit arrangement according to claim 6, in which each control circuit has a pair of terminals for receipt of the TURN ON and TURN OFF pulses, one terminal being connected to the base of the respective transistor, the other connected to the emitter thereof through the controlled rectifier device, and in which the resistance-capacitance time delay circuit is connected across the two terminals with the gate and cathode electrodes of the controlled rectifier device connected across the capacitance thereof.