Correcting errors in transmitted binary data

Claim 3

A method as defined in claim 1 comprising the preliminary step of storing each originally transmitted word at the input of the channel and wherein said steps of inverting and transmitting are performed on the word stored at the input of the channel.

Claim 4

A method as defined in claim 1 wherein the transmission channel is a parallel read-in, parallel readout memory connected to read data words out to an information register and to read data words in from the register, and said step of testing is carried out after a word has been read out to the register and while the word is in the register.

Claim 5

A method as defined in claim 3 wherein said step of inverting is carried out as the word is read out from the register, said step of transmitting is carried out by reading the inverted bits into the memory, and said step of re-inverting is carried out as the inverted bits are read out of the memory back into the register.

Claim 6

A method as defined in claim 3 wherein said step of inverting is carried out while again reading the word out from the memory to the register, said step of transmitting is carried out by reading the inverted bits from the register into the memory, and said step of re-inverting is carried out while reading the inverted bits from the memory into the register.

Claim 7

A method as defined in claim 3 wherein said step of inverting is carried out while reading the word out of the register, said step of transmitting is carried out by reading the inverted bits into the memory and subsequently reading those bits out of the memory and back into the register, and said step of re-inverting is carried out while reading the inverted bits out of the register to an external device.

Claim 8

A method as defined in claim 1 wherein each word bit is represented by an electrical signal whose value is above a discrimination threshold for one binary bit state and below the threshold for the opposite binary bit state and comprising the further step of, during said transmitting step, lowering the dircrimination threshold of each bit which, at the time of said testing step, had said one binary state, and raising the discrimination threshold of each bit which, at the time of said testing step, had said opposite binary state.

Claim 9

A method as defined in claim 1 wherein each word bit is represented by an electrical signal whose value is above a discrimination threshold for one binary bit state and below the threshold for the opposite binary bit state and comprising the further step of, duriNg said transmitting step, raising the electrical signal value of each bit which, at the time of said testing step, had said one binary state, and lowering the electrical signal value of each bit which, at the time of said testing step, had said opposite binary state.

Claim 10

Apparatus for correcting errors which appear in binary data words when their bits are transmitted in parallel over a transmission channel having one transmission path for each word bit and which are due to a fault in one transmission path, comprising, in combination: a memory containing data words to be transmitted and arranged to read out the bits of such word in parallel; error recognition means connected to the output of the channel for producing an error signal upon receipt, from the channel, of a word containing an error; first parallel switch means connected between said memory and the inputs of the channel for delivering the bits of a word stored in said memory in parallel to the channel paths; bit inversion means connected to the output of the channel for inverting each bit of a word appearing at the channel output; and second parallel switch means having output terminals and signal inputs connected to the channel outputs and to the outputs of said inversion means, said second switch means also having a control input connected to the output of said error recognition means for controlling the operation of said second switch means for placing said second switch means in a first state in which the channel outputs are connected to said output terminals when no error signal is produced by said error recognition means and in a second state in which said inversion means outputs are connected to said output terminals when an error signal is produced by said error recognition means.

Claim 11

Apparatus for correcting errors which appear in binary data words when their bits are transmitted in parallel over a transmission channel having one transmission path for each word bit and which are due to a fault in one transmission path, comprising, in combination: a memory containing data words to be transmitted and arranged to read out the bits of such word in parallel; error recognition means connected to the output of the channel for producing an error signal upon receipt, from the channel, of a word containing an error; first parallel switch means connected between said memory and the inputs of the channel for delivering the bits of a word stored in said memory in parallel to the channel paths; bit inversion means connected to the output of the channel for inverting each bit of a word appearing at the channel output; and second parallel switch means having output terminals and signal inputs connected to the channel outputs and to the outputs of said inversion means, said second switch means also having a control input connected to the output of said error recognition means for controlling the operation of said second switch means for placing said second switch means in a first state in which the channel outputs are connected to said output terminals when no error signal is produced by said error recognition means and in a second state in which said inversion means outputs are connected to said output terminals when an error signal is produced by said error recognition means.

Claim 12

An arrangement as defined in claim 9 further comprising second bit inversion means connected between said memory and said first switch means for inverting each bit of a word read out of said memory, and wherein said first switch means has a control input connected to the output of said error recognition means for placing said first switch means in a first state in which said memory is connected directly to the inputs of the channel when no error signal is produced by said error correction means, and a second state in which said second bit inversion means is connected in series between said memory and the inputs of the channel when an error signal is produced by said error recognition means.

Claim 13

Apparatus for correcting errors which appear in binary data words when their bits are transmitted in parallel over a transmission channel having one transmission path for each word bit and which are due to a fault in one transmission path, comprising, in combination: a memory unit having a plurality of addressable data word storage locations and arranged for the parallel read-in and readout of a data word at each location, a selected storage location of said unit constituting the transmission channel; a data word register connected for parallel read-in and readout of data words; first parallel switch means selectively connecting the inputs of said register to the outputs of said memory or to external data word input terminals; read-in means connecting the outputs of said register to the inputs of said memory unit; switchable bit inversion means connected in series between said memory unit and said register and switchable between a first state in which it permits the passage of a word with its bits unaltered and a second state in which it inverts each bit of a word passing therethrough, error recognition means connected to the output of said register for producing an error signal at its output upon the appearance of a data word containing an error in said register; logic circuit means having an input connected to the output of said error recognition means and responsive to the signal at its input to be switchable between a first state in which it normally produces an ouTput signal when no error signal is being produced by said error recognition means, and a second state in which it produces no output signal when an error signal is being produced by said error recognition means; temporary storage means connected to store the output signal produced by said logic circuit means; means providing a succession of periodic signal pulses including, in order, first, second and third signal pulses; and counter means having one input connected to said temporary storage means, a second input connected to receive such periodic signal pulses, and an output at which a count signal appears when a signal pulse is applied to its said second input and no signal is being stored by said storage means, the output of said counter means being connected to said logic circuit means and to a control input of said bit inversion means for placing said bit inversion means in its second state when a count signal appears at said counter means output.

Claim 14

Apparatus for correcting errors which appear in binary data words when their bits are transmitted in parallel over a transmission channel having one transmission path for each word bit and which are due to a fault in one transmission path, comprising, in combination: a memory unit having a plurality of addressable data word storage locations and arranged for the parallel read-in and readout of a data word at each location, a selected storage location of said unit constituting the transmission channel; a data word register connected for parallel read-in and readout of data words; first parallel switch means selectively connecting the inputs of said register to the outputs of said memory or to external data word input terminals; read-in means connecting the outputs of said register to the inputs of said memory unit; switchable bit inversion means connected in series between said memory unit and said register and switchable between a first state in which it permits the passage of a word with its bits unaltered and a second state in which it inverts each bit of a word passing therethrough, error recognition means connected to the output of said register for producing an error signal at its output upon the appearance of a data word containing an error in said register; logic circuit means having an input connected to the output of said error recognition means and responsive to the signal at its input to be switchable between a first state in which it normally produces an ouTput signal when no error signal is being produced by said error recognition means, and a second state in which it produces no output signal when an error signal is being produced by said error recognition means; temporary storage means connected to store the output signal produced by said logic circuit means; means providing a succession of periodic signal pulses including, in order, first, second and third signal pulses; and counter means having one input connected to said temporary storage means, a second input connected to receive such periodic signal pulses, and an output at which a count signal appears when a signal pulse is applied to its said second input and no signal is being stored by said storage means, the output of said counter means being connected to said logic circuit means and to a control input of said bit inversion means for placing said bit inversion means in its second state when a count signal appears at said counter means output.

Claim 15

An arrangement as defined in claim 11 wherein: there are two of said bit inversion means one of which is connected in series between the output of said register and the input of said memory unit and the other of which is connected in series between the output of said memory unit and the input of said register; and said counter has a first output and a second output both connected to said logic circuit means and is arranged for producing, when no signal is stored by said storage means, a count signal at only said first output when such first signal pulse is applied to its said second input, a count signal at only said second output when such second signal pulse is applied to its said second input, and a count signal at both of said outputs when such third signal pulse is applied to its said second input, said second output being connected to the control input of said other of said bit inversion means for placing that bit inversion means in its second state only when a count signal appears at said second output; and said arrangement further comprises: a first ANDNOT member having a direct input connected to said first output of said counter means, a negated input connected to said second output of said counter means, and an output connected to the control input of said one bit of said bit inversion means for placing that bit inversion means in its said second state when a signal appears at said output of said first ANDNOT member; a second ANDNOT member having a direct input connected to receive a periodic pulse before each periodic signal pulse received by said counter means second input, a negated input connected to said first output of said counter, and an output connected to a control input of said register for causing the contents of said register to be read out when a signal appears at said output of said second ANDNOT member; and second logic circuit means connected to control the read-in and readout modes of said memory unit and having a control input connected to said first output of said counter for changing the reading mode of said memory unit upon the appearance of a count signal at said first output of said counter means.

Claim 16

An arrangement as defined in claim 11 wherein: said bit inversion means is connected in series between the output of said memory unit and the input of said register; and said counter has a first output and a second output both connected to said logic circuit means and is arranged for producing, when no signal is stored by said storage means, a count signal at only said first output when such first signal pulse is applied to its said second input, a count signal at only said second output when such second signal pulse is applied to its said second input, and a count signal at both of said outputs when such third signal pulse is applied to its said second input; and said arrangement further comprises an OR member having two inputs each connected to a respective one of said outputs of said counter means and an outpuT connected to the control input of said bit inversion means for placing said bit inversion means in its second state when a count signal appears at either output of said counter means.

Claim 17

An arrangement as defined in claim 11 wherein said bit inversion means is connected in series between the output of said register and the input of said memory, and said arrangement further comprises: second temporary storage means connected to said counter means output to store the count signal appearing thereat; an ORNOT member having a direct input connected to said second temporary storage means, a negated input connected to said first-recited temporary storage means, and an output connected to the control input of said bit inversion means for placing said bit inversion means in its second state when a signal appears at said output of said ORNOT member; and a reset line connected to both of said temporary storage means for applying a reset pulse thereto for erasing their contents prior to each periodic signal pulse applied to said second input of said counter means.

Claim 18

An arrangement as defined in claim 11 further comprising; a readout device connected to the output of said memory unit and composed of a plurality of threshold amplifiers each connected in one transmission path of said memory unit output for producing a word bit having one binary state when it receives an electrical signal whose value is above a discrimination threshold and a word bit having the opposite binary state when it receives an electrical signal whose value is below that discrimination threshold; and adjusting means connected to be controlled by said error recognition means for increasing the difference between the electrical signal and the threshold associated with each transmission path.

Claim 19

An arrangement as defined in claim 15 wherein said adjusting means are connected to the output of said register for increasing such difference in accordance with the value of the bits stored in said register.

Claim 20

An arrangement as defined in claim 16 wherein said adjusting means comprises for each transmission path: a control device connected to the output of said error recognition means and to the associated bit output of said register, and having two outputs; two switching elements each connected to a respective output of said control device to have its switching state controlled by the signal appearing at such output; a voltage divider having its output connected to the associated threshold amplifier for applying a voltage which determines the amplifier threshold value; and two resistors each connected to a respective switching element, each said element and its associated resistor forming a series arrangement connected across said voltage divider.

Claim 21

An arrangement as defined in claim 16 wherein the amplitude of each bit-representing electrical signal produced by said memory unit during readout is determined by the value of the excitation current applied to an associated bit storage element, and said adjusting means comprises, for each transmission path: two switch elements connected to be controlled by the output of said error recognition device and the associated bit output of said register; two resistors each connected in series with a respective switch element in the excitation current path of the associated bit storage element; and a further resistor connected in parallel with the series branches composed of said switch elements and their associated resistors.