Tri-stable state circuitry for digital computers

Claim 1

A tri-stable circuit having input terminals and three output terminals, said circuit being adapted to assume and maintain a stable output memory of signals constituting a binary input condition representative of each of said inputs at a corresponding one of said outputs, during and after application of said signals to said inputs, comprising the combination of: three current control devices, each having first and second principal current carrying electrodes and at least one control electrode for controlling the current flowing between said principal electrodes; a common connection among corresponding first ones of said principal electrodes, said second electrodes each being connected to a power supply source through a separate load impedance element; triggering means comprising a regenerative direct coupled current path between said second principal electrode of each of first and second ones of said current control devices and said control electrode of the other of said first and second control devices; terminal means including three input terminals connected one to said control electrode of each of said current control devices, and three output terminals connnected one to each of said second principal electrode of each of said current control devices, whereby said binary inputs may be applied to produce said stablE output memory; first biasing means comprising a first bias element having a predetermined voltage drop characteristic inserted in the current path between said first principal electrode of the third of said current control devices and said common connection of said principal electrodes; and second biasing means comprising a pair of second bias elements connected in series between said second principal electrodes of said first and second current control devices, the mid-point of said second bias elements being connected to said control electrode of said third current control device.