Reversible ternary counter

Claim 2

In a ternary digital counter, a first input terminal for receiving an up counting control signal, a second input terminal for receiving a down counting control signal, counting means having three discrete output states, said counting means being adapted for cyclically advancing through said output states in both positive and negative directions, means for delivering clock pulses to said counting means, steering means connected to said input terminals and to said counting means for conditioning said counting means to advance in the positive direction in response to said clock pulses when said up counting control signal is present and advance in the negative direction in response to said clock pulses when said down counting control signal is present, means for resetting said counting means to a predetermined one of said output states, and means for generating a carry pulse when said counting means advances between predetermined output states and for generating a rounding carry pulse when said counting means is reset to said predetermined one of said output states from a predetermined other of said states.

Claim 3

A ternary counter as in claim 1 wherein said counting means includes first and second flip-flop means having toggle inputs to which said clock pulses are applied, control inputs to which said steering means is connected, and outputs capable of assuming high and low logic levels to provide the three discrete output states.

Claim 4

A ternary counter having a plurality of stages, each of said stages being of the character defined by claim 1, the clock input terminal of the counting means of each successive stage being connected for receiving the carry pulses from the preceding stage.

Claim 5

A ternary counter as in claim 1 wherein the means for generating a carry pulse includes a logic element having a predetermined propagation time, said element being connected in such manner that its propagation time determines the width of said carry pulse.

Claim 6

A ternary counter as in claim 4 wherein said counting means includes flip-flop means having a first output which is high when said counting means is in its highest output state and low when said counting means is in its lowest output state, said logic element being an NOR gate having a first input connected to the first output of said flip-flop means and a second input connected to be continuously low, said means for generating a carry pulse also including a first control gate connected for receiving inputs from the first output of said flip-flop means and from the output of the first named NOR gate.

Claim 7

A ternary counter as in claim 5 wherein said flip-flop means also has a second output which is the inverse of said first output wherein said means for generating a carry pulse also includes an additional NOR gate and a second control gate connected to said second output and to each other in the same manner in which the NOR and control gates are connected, means connecting the first and second input termiNals of said counter to the control gates for selectively enabling said gates in accordance with the up and down counting control signals, and the output gate means connected for receiving inputs from the outputs of said control gates, the carry pulse appearing at the output of said output gate means.

Claim 8

In a ternary digital counter, a first input terminal for receiving an up counting control signal, a second input terminal for receiving a down counting control signal, counting means including first and second flip-flop means each having outputs capable of assuming high and low logic levels connected together to provide three discrete output states, said counting means being adapted for cyclically advancing through said output states in both positive and negative directions, means for delivering clock pulses to said counting means, steering means connected to said input terminals and to said counting means for conditioning said counting means to advance in the positive direction in response to said clock pulses when said upcounting control signal is present and to advance in the negative direction in response to said clock pulses when said down counting control signal is present, decoder means connected to the outputs of said flip-flop means for converting the logic levels of said outputs to a three-bit output signal, said decoder means including three output terminals each carrying one of the three bits in said output signal, means connecting two of said output terminals directly to the outputs of said flip-flop means, and logic means connected between the remaining output terminal and the outputs of said flip-flop means such that the bit carried by said remaining terminal is the logic NOR equivalent of the bits carried by the two directly connected output terminals.

Claim 9

In a ternary digital counter, a first input terminal for receiving an up counting control signal, a second input terminal for receiving a down counting control signal, counting means including first and second flip-flop means each having outputs capable of assuming high and low logic levels connected together to provide three discrete output states, said counting means being adapted for cyclically advancing through said output states in both positive and negative directions, means for delivering clock pulses to said counting means, steering means connected to said input terminals and to said counting means for conditioning said counting means to advance in the positive direction in response to said clock pulses when said upcounting control signal is present and to advance in the negative direction in response to said clock pulses when said down counting control signal is present, decoder means connected to the outputs of said flip-flop means for converting the logic levels of said outputs to a three-bit output signal, said decoder means including three output terminals each carrying one of the three bits in said output signal, means connecting two of said output terminals directly to the outputs of said flip-flop means, and logic means connected between the remaining output terminal and the outputs of said flip-flop means such that the bit carried by said remaining terminal is the logic NOR equivalent of the bits carried by the two directly connected output terminals.

Claim 10

A ternary counter as in claim 7 wherein each of said flip-flop means has both normal and inverted outputs and said steering means includes first and second sections, said first section comprising NOR gate means connected for receiving inputs from said first and second input terminals and delivering an output to the control input of said first flip-flop means, and said second section comprising NOR gate means connected for receiving inputs from said first and second input terminals and from the outputs of said first flip-flop means and delivering an output to the control input of said second flip-flop means.

Claim 11

A ternary counter as in claim 8 together with feedback means connecting the outputs of said second flip-flop means as inputs to the first section of said steering means, said feedback means serving to prevent said counting means from having an illegal output state.

Claim 12

In bidirectional ternary counting apparatus: means for receiving input signals; means for receiving an up-down control signal; reversible counting means having low, intermediate and high states; means for advancing the counting means from the low state to the intermediate state, from the intermediate state to the high state and from the high state to the low state in response to input signals received when the control signal indicates an up-counting condition; means for advancing the counting means from the low state to the high state, from the high state to the intermediate state and from the intermediate state to the low state in response to input signals received when the control signal indicates a down counting condition; means for generating a carry signal when said counting means is advanced from the high state to the low state or from the low state to the high state; means for resetting the counting means to the low state; and means for generating a rounding carry pulse when the counting means is reset to the low state from the high state.

Claim 13

In bidirectional ternary counting apparatus: means for receiving input signals; means for receiving an up-down control signal; reversible counting means having low, intermediate and high states; means for advancing the counting means from the low state to the intermediate state, from the intermediate state to the high state and from the high state to the low state in response to input signals received when the control signal indicates an up-counting condition; means for advancing the counting means from the low state to the high state, from the high state to the intermediate state and from the intermediate state to the low state in response to input signals received when the control signal indicates a down counting condition; means for generating a carry signal when said counting means is advanced from the high state to the low state or from the low state to the high state; means for resetting the counting means to the low state; and means for generating a rounding carry pulse when the counting means is reset to the low state from the high state.

Claim 14

Bidirectional ternary counting apparatus as in claim 10 together with means for generating an output signal pattern signifying the low, intermediate and high output states of the counting means.