← Back to Patent Explorer
US3662230A Expired / Lapsed US ⏱️ 0.0 years remaining

A semiconductor interconnecting system using conductive patterns bonded to thin flexible insulating films

Assignee: Texas Instruments Inc
•
Filing: 1970-11-30
•
Granted: 1972-05-09
•
Expires: 1990-11-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A highly reliable, low cost packaging system for one or more semiconductor chips each having metal contact pads on at least one face. A rigid support is provided for the semiconductor chip and also the large leads which are used to connect the packaged device in an external circuit. A set of thin metallic film strips are bonded to a thin flexible dielectric sheet for support. The set of metal strips interconnects the contact pads on the semiconductor chips and selected leads to electrically interconnect the semiconductor device and the leads. Where a plurality of semiconductor devices are used, a plurality of dielectric sheets can be stacked and electrical connections made between the different layers of metal film strips through openings in the dielectric sheets. Several processes for assembling the packages are also described.

Inventors

  • 👤 James O Redwantz

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 16:42
CPC Classifications
H; H10; H10W; H10W99/00; H10W70/00; H10W70/60; H10W70/611; H10W70/614; H10W70/67; H10W70/688; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/132; H10W76/40; H10W90/00; H10W90/401; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 219 words
A hermeticAlly sealed semiconductor package for an electrical system, comprising in combination: a. a rigid insulating support having major surfaces and edges; b. a plurality of spaced conductor pins transversely extending through and secured to said rigid insulating support; c. a plurality of semiconductor components secured to one major surface of said rigid insulating support in a preselected spaced relationship; d. a relatively thin, flexible insulating support being relatively thin with respect to said rigid insulating support and having 1. planar surface; 2. a plurality of selectively spaced bonding pads formed on said one planar surface; 3. a plurality of selectively spaced passive elements formed on said one planar surface; and 4. a plurality of selectively spaced openings formed in said flexible insulating support in respective co-axial relationship with said conductor pins, with said other planar surface abuting said one major surface of said rigid insulating support; e. a semiconductor device having selectively spaced contact pads formed thereon, said contact pads being selectively secured to said bonding pads on said flexible insulating support; and f. housing means secured to said rigid insulating support and overlying said one major surface thereof for hermetically sealing said package; wherein g. said conductor pins, semiconductor components, passive elements and semiconductor device are selectively interconnected by said conductive pattern to form said electrical system.
Claim 2
Dependent Claim 219 words
A hermeticAlly sealed semiconductor package for an electrical system, comprising in combination: a. a rigid insulating support having major surfaces and edges; b. a plurality of spaced conductor pins transversely extending through and secured to said rigid insulating support; c. a plurality of semiconductor components secured to one major surface of said rigid insulating support in a preselected spaced relationship; d. a relatively thin, flexible insulating support being relatively thin with respect to said rigid insulating support and having 1. planar surface; 2. a plurality of selectively spaced bonding pads formed on said one planar surface; 3. a plurality of selectively spaced passive elements formed on said one planar surface; and 4. a plurality of selectively spaced openings formed in said flexible insulating support in respective co-axial relationship with said conductor pins, with said other planar surface abuting said one major surface of said rigid insulating support; e. a semiconductor device having selectively spaced contact pads formed thereon, said contact pads being selectively secured to said bonding pads on said flexible insulating support; and f. housing means secured to said rigid insulating support and overlying said one major surface thereof for hermetically sealing said package; wherein g. said conductor pins, semiconductor components, passive elements and semiconductor device are selectively interconnected by said conductive pattern to form said electrical system.
Claim 3
Dependent Claim 13 words
a plurality of selectively spaced bonding pads formed on said one planar surface;
Claim 4
Dependent Claim 13 words
a plurality of selectively spaced bonding pads formed on said one planar surface;
Claim 5
Dependent Claim 53 words
The semiconductor device is in accordance with claim 1 further including at least two electrically conductive regions disposed on opposite sides of the said flexible insulating support, said regions having substantial overlap, with electrical interconnections between said electrically conductive regions and said semiconductor device, whereby said two electrically conductive regions form a capacitor.
Claim 6
Dependent Claim 63 words
The hermetically sealed semiconductor package of claim 1 and further including: a. a plurality of said flexible insulating supports, each of which has its opening in respective coaxial relationship with said conductor pins; wherein b. said conductor pins, semiconductor components, passive elements, and semiconductor device of said rigid insulating support and said flexible insulating supports are selectively interconnected to form said electrical system.
Claim 7
Dependent Claim 14 words
a plurality of selectively spaced passive elements formed on said one planar surface; and
Claim 8
Dependent Claim 14 words
a plurality of selectively spaced passive elements formed on said one planar surface; and
Claim 9
Dependent Claim 35 words
A semiconductor package in accordance with claim 3,wherein at least one of said flexible insulating supports is substantially covered with a layer of electrically conductive material, said electrically conductive material serving as a ground plane.
Claim 10
Dependent Claim 107 words
a plurality of selectively spaced openings formed in said flexible insulating support in respective co-axial relationship with said conductor pins, with said other planar surface abuting said one major surface of said rigid insulating support; e. a semiconductor device having selectively spaced contact pads formed thereon, said contact pads being selectively secured to said bonding pads on said flexible insulating support; and f. housing means secured to said rigid insulating support and overlying said one major surface thereof for hermetically sealing said package; wherein g. said conductor pins, semiconductor components, passive elements and semiconductor device are selectively interconnected by said conductive pattern to form said electrical system.
Claim 11
Dependent Claim 107 words
a plurality of selectively spaced openings formed in said flexible insulating support in respective co-axial relationship with said conductor pins, with said other planar surface abuting said one major surface of said rigid insulating support; e. a semiconductor device having selectively spaced contact pads formed thereon, said contact pads being selectively secured to said bonding pads on said flexible insulating support; and f. housing means secured to said rigid insulating support and overlying said one major surface thereof for hermetically sealing said package; wherein g. said conductor pins, semiconductor components, passive elements and semiconductor device are selectively interconnected by said conductive pattern to form said electrical system.

References Cited (Backward Citations)

US3256465A Cited
US3363146A Cited
US3311798A Cited
US3262023A Cited
US3388301A Cited
US3387365A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-09 1975-11-08 1976-05-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-09 1979-11-08 1980-05-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-09 1983-11-08 1984-05-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag