Electronic phasing and synchronizing circuit for facsimile recorders

Claim 1

In a system for recording received facsimile video signals transmitted from satellites, apparatus for generating a sweep signal which is in synchronism and in phase with said facsimile video signals, said facsimile video signals comprising a video baseband signal amplitude modulated onto a subcarrier signal, having a frequency F, said facsimile video signals having a phasing bar at the beginning of each line thereof, said phasing bar having an amplitude substantially equal to maximum white with respect to said video baseband signal and having a selectively predetermined pulsewidth greater than t1 but less than t2 where t1 and t2 are measured from zero, said apparatus comprising, input terminal means for receiving said facsimile video signals, automatic gain control means connected to said input terminal means for maintaining said phasing bar amplitude substantially constant, demodulator means for receiving said facsimile video signals having gain-controlled phasing bars and for producing said video baseband signals, video recorder means for receiving said video baseband signals, first amplitude threshold means for receiving said video baseband signals and for producing an output pulse when the amplitude oF said video baseband signals is substantially equal to said phasing bar amplitude and having a width substantially equal to the time said amplitudes are equal, integrator means for receiving said output pulse and for producing a width detection signal having a magnitude which increases linearly with respect to time, first comparator means for receiving said width detection signal and for producing a first logic signal when the magnitude of said width detection signal corresponds to a width substantially equal to said t1, second comparator means for receiving said width detection signal and for producing a second logic signal when the magnitude of said width detection signal corresponds to a width substantially equal to said t2, said first and second logic signals being of like polarity, first pulse delay means for receiving said first logic signal and for producing a time-delayed first logic signal having a delay time, with respect to said second logic signal, equal to t2-t1, logic gate means for receiving said time-delayed first logic signal and said second logic signal and for producing a phasing pulse when both of said signals are received thereby indicating the presence of said phasing bar in said video baseband signals, second pulse delay means for receiving said phasing pulse and for producing a time-delayed phasing pulse having a delay time substantially equal to one-half the pulsewidth of said phasing bar, first dump circuit means for receiving said time-delayed phasing pulse and for dumping said integrater means each time said phasing bar is received, oscillator means for receiving said subcarrier and being responsive thereto to produce a square-wave output having the same frequency as said subcarrier, sweep generator means for receiving said square-wave output and for producing a linear ramp sweep output in response thereto, frequency divider means for receiving said square-wave output and for producing a divided frequency output at a rate equal to F/N, where N 1, 2, 3, - - - , second dump circuit means for receiving said divided frequency output and for dumping said sweep generator means at said divided frequency output rate, whereby said sweep output rate is substantially equal to F/N; and, said frequency divider means further including means for receiving said phasing pulse and for re-setting said sweep generator means whereby said sweep output is in phase with said phasing bar and further including means for receiving said time-delayed phasing pulse whereby said sweep output is in phase substantially with the middle of said phasing bar.