US3660837A
Expired / Lapsed
US
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Method and device for binary-decimal conversion
Assignee: Individual
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Filing: 1970-08-10
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Granted: 1972-05-02
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Expires: 1990-08-10
Abstract
Abstract A method for conversion of a binary number to the decimal system utilizing division of the binary number by 2 with storage in memory of the remainder corresponding to the binary figure of smaller order of the number and a sequence of operations on the quotient to effect division by 5 so as to obtain at each sequence a number associated with the quotient of successive divisions by 10 of the number to be converted, and a number associated with the remainder of this same division, the remainder then constituting a decimal figure of the converted number. A conversion device constituted by a counter of elementary times or a clock, an input register with n bits positions, a main shifting register with n + 2 bits positions, a correction shifting register with four positions of bits for formation of the correction in finding the true quotient of division by 5, a series adder with variable connections and a carry-over trigger device for establishing the above connections during the course of the cycle of operation and for sequencing the device, a programming device and an output register for presentation of the decimal figures.
Inventors
- 👤 Jean Pierre Chinal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:16
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/02; H03M7/12
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
427 words
A device for converting a whole number S'' expressed in the binary system and with a maximum of n bits represented by the expression (S''n 1 S''n 2 . . . S''2 S''1 S''0) to its equivalent decimal number represented by the expression Dm 1 Dm 2 . . . D2 D1 D0, comprising a main shift register having n + 2 bit positions represented by the expression Pn 1 Pn . . . P2 P1 P0; a correction shift register having four bit positions; an adderresiduator means having inputs from said registers and an output feedback loop to said main shift register and including a carryover trigger unit; an output circuit having an input from said adder-residuator, an output to said correction shift register and including a logical inscription unit and an output register; and switching and programming means governing the sequence of operation of the above elements, wherein, for operation, the number S'' is entered in the main shift register with Sk in position Pk for k 0 to n inclusive and 0 in positions Pn 1 and Pn and a two part cycle is commenced, in the first part of which S'' is divided by two by a shift of one position throughout the main shift register to give a number S, with remainder S''0 being entered in said output register, the number S is applied in sequence lowest order digit first to the adder-residuator means which provides a ''''pseudo-quotient'''' represented by The expression X (Xn 1 Xn . . . X1 X0) where Xk + Sk + Xk 2 + Rk 1 (modulo 2), ''''carry-over'''' Rk Maj (Xk, Xk 2, Rk 1) and X 1, X 2 0, R 1 0, X is fed back into said main shift register and Xn 1, Xn and Rn 1, forming a residue, are entered in said inscription unit which, in accordance with their values and the number n provides a remainder R for division of S by 5 to give a remainder R'' 2R + S''0 for division of S'' by 10 in said output register, and sets a correction sequence of four digits in said correction shift register, and in the second part of which cycle pseudo-quotient X is added in the adder-residuator to the correction number consisting of a cyclic sequence of said four digits to give a true quotient Q which is entered in said main shift register, the cycles being repeated with Q being operated on as S'' to give successive remainders R '' D0, D1 . . . Dm 1.
Claim 2
Independent Claim
427 words
A device for converting a whole number S'' expressed in the binary system and with a maximum of n bits represented by the expression (S''n 1 S''n 2 . . . S''2 S''1 S''0) to its equivalent decimal number represented by the expression Dm 1 Dm 2 . . . D2 D1 D0, comprising a main shift register having n + 2 bit positions represented by the expression Pn 1 Pn . . . P2 P1 P0; a correction shift register having four bit positions; an adderresiduator means having inputs from said registers and an output feedback loop to said main shift register and including a carryover trigger unit; an output circuit having an input from said adder-residuator, an output to said correction shift register and including a logical inscription unit and an output register; and switching and programming means governing the sequence of operation of the above elements, wherein, for operation, the number S'' is entered in the main shift register with Sk in position Pk for k 0 to n inclusive and 0 in positions Pn 1 and Pn and a two part cycle is commenced, in the first part of which S'' is divided by two by a shift of one position throughout the main shift register to give a number S, with remainder S''0 being entered in said output register, the number S is applied in sequence lowest order digit first to the adder-residuator means which provides a ''''pseudo-quotient'''' represented by The expression X (Xn 1 Xn . . . X1 X0) where Xk + Sk + Xk 2 + Rk 1 (modulo 2), ''''carry-over'''' Rk Maj (Xk, Xk 2, Rk 1) and X 1, X 2 0, R 1 0, X is fed back into said main shift register and Xn 1, Xn and Rn 1, forming a residue, are entered in said inscription unit which, in accordance with their values and the number n provides a remainder R for division of S by 5 to give a remainder R'' 2R + S''0 for division of S'' by 10 in said output register, and sets a correction sequence of four digits in said correction shift register, and in the second part of which cycle pseudo-quotient X is added in the adder-residuator to the correction number consisting of a cyclic sequence of said four digits to give a true quotient Q which is entered in said main shift register, the cycles being repeated with Q being operated on as S'' to give successive remainders R '' D0, D1 . . . Dm 1.
Claim 3
Dependent Claim
41 words
A device as claimed in claim 1, wherein bit positions Pn 1 and Pn have connections to said inscription unit whereby the digits Xn 1 and Xn are transferred to that unit when X is entered in the main shift register.
Claim 4
Dependent Claim
57 words
A device as claimed in claim 2, wherein n 4p where p is an integer and said inscription unit includes four AND gates having a common control from the switching and programming means and respective inputs for Xn 1 , Xn 1, Xn, Xn, the four outputs being to the four bit positions of the correction register.
Claim 5
Dependent Claim
27 words
A device as claimed in claim 1, and further comprising an input register having n bit positions for the number S'' connected to said main shift register.
Claim 6
Dependent Claim
27 words
A device as claimed in claim 3, and further comprising an input register having n bit positions for the number S'' connected to said main shift register.
Claim 7
Dependent Claim
22 words
A device as claimed in claim 1, and further comprising an output memory connected to said output register for storing remainders R''.
Claim 8
Dependent Claim
22 words
A device as claimed in claim 5, and further comprising an output memory connected to said output register for storing remainders R''.
Claim 9
Dependent Claim
36 words
A device as claimed in claim 1, wherein said adder-residuator is adapted to provide Maj (Xk, Xk 2, Rk 1) by evaluating Xk Xk 2 + Rk 1 Xk + Rk 1 Xk 2 (modulo 2).
Claim 10
Dependent Claim
36 words
A device as claimed in claim 7, wherein said adder-residuator is adapted to provide Maj (Xk, Xk 2, Rk 1) by evaluating Xk Xk 2 + Rk 1 Xk + Rk 1 Xk 2 (modulo 2).
Claim 11
Dependent Claim
36 words
A device as claimed in claim 1, wherein said adder-residuator is adapted to provide Maj (Xk, Xk 2, Rk 1) by evaluating Sk Xk 2 + Xk 2 Rk 1 + Sk Rk 1 (modulo 2).
Claim 12
Dependent Claim
36 words
A device as claimed in claim 7, wherein said adder-residuator is adapted to provide Maj (Xk, Xk 1, Rk 1) by evaluating Sk Xk 2 + Xk 2 Rk 1 + Sk Rk 1 (modulo 2).
Claim 13
Dependent Claim
71 words
A device as claimed in claim 1, wherein said output register includes fOur trigger units, three of which receive the remainder R in binary form r3 r2 r1 from said inscription unit to whose inputs is applied the residue, and the other one of which receives S''0, said trigger units giving as an output the binary version of the decimal remainder R'' under the control of the switching and programming means.
Claim 14
Dependent Claim
71 words
A device as claimed in claim 11, wherein said output register includes four trigger units, three of which receive the remainder R in binary form r3 r2 r1 from said inscription unit to whose inputs is applied the residue and the other one of which receives S''0, said trigger units giving as an output the binary version of the decimal remainder R'' under the control of the switching and programming means.
Claim 15
Dependent Claim
89 words
A device as claimed in claim 1, wherein a zero quotient detecting device is provided including a gate for the quotient open during the second part of the cycle, a trigger unit responsive to the successive quotient signals to change its condition when a non-zero signal occurs and a gate for the output of the trigger unit controlled by an end of cycle signal to give an output at that time indicative of the condition of the trigger unit and hence of the presence of non-zeros in the quotient.
Claim 16
Dependent Claim
89 words
A device as claimed in claim 13, wherein a zero quotient detecting device is provided including a gate for the quotient open during the second part of the cycle, a trigger unit responsive to the successive quotient signals to change its condition when a non-zero signal occurs and a gate for the output of the trigger unit controlled by an end of cycle signal to give an output at that time indicative of the condition of the trigger unit and hence of the presence of non-zeros in the quotient.
Claim 17
Dependent Claim
62 words
A device as claimed in claim 1, wherein said carry-over trigger unit in the adder-residuator device is a memory for one bit whose contents Rk 1 entered during the cycle are applied to the adder for determining Xk and the residuator for determining Rk during the succeeding cycle, Rk being entered in said memory in the second part of said succeeding cycle.
Claim 18
Dependent Claim
62 words
A device as claimed in claim 15, wherein said carry-over trigger unit in the adder-residuator device is a memory for one bit whose contents Rk 1 entered during the cycle are applied to the adder for determining Xk and the residuator for determining Rk during the succeeding cycle, Rk being entered in said memory in the second part of said succeeding cycle.
Claim 19
Dependent Claim
132 words
A device as claimed in claim 1, wherein the adder-residuator has an auxiliary register, and the switching and programming means is adapted to govern operation in three part cycles, in the first part of which S is determined from S'' (S'' 2S + S''0) and stored in the main shift register and remainder Rof the division by 5 of S is determined and stored in the auxiliary register while R'' 2R + S''0 is available from the output circuit, in the second part of which R is subtracted from S in the adder-residuator and S-R is stored in the main shift register, and in the third part of which S-R/5 is determined to give the quotient Q which is entered in the main shift register for the next succeeding cycle of operations.
Claim 20
Dependent Claim
133 words
A device as claimed in claim 17, wherein the adder-residuator has an auxiliary register, and the switching and programming means is adapted to govern operation in three part cycles, in the first part of which S is determined from S'' (S'' 2S + S''0) and stored in the main shift register and remainder R of the division by 5 of S is determined and stored in the auxiliarY register while R'' 2R + S''0 is available from the output circuit, in the second part of which R is subtracted from S in the adder-residuator and S-R is stored in the main shift register, and in the third part of which S-R/5 is determined to give the quotient Q which is entered in the main shift register for the next succeeding cycle of operations.
Claim 21
Dependent Claim
126 words
A device as claimed in claim 1, with the modification that the adder-residuator has an associated subtraction unit and auxiliary register, and the switching and programming means is adapted to govern operation in two part cycles, in the first part of which S is determined from S'' (S'' 2S + S''0) and stored in the main shift register and remainder R of the division by 5 of S is determined and stored in the auxiliary register, while R'' 2R + S''0 is available from the output circuit, and in the second part of which the outputs of the main shift and auxiliary registers are applied to the subtraction unit which delivers S-R to the adder-residuator which in turn delivers Q S-R/5 to the main shift register.
Claim 22
Dependent Claim
126 words
A device as claimed in claim 17, with the modification that the adder-residuator has an associated subtraction unit and auxiliary register, and the switching and programming means is adapted to govern operation in two part cycles, in the first part of which S is determined from S'' (S'' 2S + S''0) and stored in the main shift register and remainder R of the division by 5 of S is determined and stored in the auxiliary register, while R'' 2R + S''0 is available from the output circuit, and in the second part of which the outputs of the main shift and auxiliary registers are applied to the subtraction unit which delivers S-R to the adder-residuator which in turn delivers Q S-R/5 to the main shift register.
Claim 23
Dependent Claim
87 words
A device as claimed in claim 1, with the modification that the adder-residuator has an associated subtraction unit and a remainder determining system, such as a further adder-residuator, and the switching and programming means is adapted to govern operation in a single part cycle in which S is determined from S'' (S'' 2S + S''0), remainder R of the division by 5 of S is determined by said adder-residuator and S-R is applied to the remainder determining system which delivers Q S-R/5 to the main shift register.
Claim 24
Dependent Claim
87 words
A device as claimed in claim 17, with the modification that the adder-residuator has an associated subtraction unit and a remainder determining system, such as a further adder-residuator, and the switching and programming means is adapted to govern operation in a single part cycle in which S is determined from S'' (S'' 2S + S''0), remainder R of the division by 5 of S is determined by said adder-residuator and S-R is applied to the remainder determining system which delivers Q S-R/5 to the main shift register.
Claim 25
Dependent Claim
79 words
A device as claimed in claim 1, wherein the adder-residuator has an associated adder and the switching and programming means is adapted to govern operation in a single part cycle in which S is determined from S'' (S'' 2S + S''0) and the pseudo-quotient is produced by the adder-residuator and added to the correction sequence derived from it in said associated adder, the resultant quotient being entered in said main shift register for the next succeeding cycle of operations.
Claim 26
Dependent Claim
79 words
A device as claimed in claim 17, wherein the adder-residuator has an associated adder and the swItching and programming means is adapted to govern operation in a single part cycle in which S is determined from S'' (S'' 2S + S''0) and the pseudo-quotient is produced by the adder-residuator and added to the correction sequence derived from it in said associated adder, the resultant quotient being entered in said main shift register for the next succeeding cycle of operations.
Claim 27
Dependent Claim
30 words
A device as claimed in claim 1, wherein n adder-residuators are provided in parallel associated with bit positions Pn 1 Pn . . . P2, of the main shift register.
Claim 28
Dependent Claim
30 words
A device as claimed in claim 25, wherein n adder-residuators are provided in parallel associated with bit positions PN 1 PN . . . P2, of the main shift register.
Claim 29
Dependent Claim
77 words
A device as claimed in claim 1, wherein there are provided m units including an adder-residuator and an adder corresponding to the m decimal digits, the adder-residuator Ri being arranged to give the remainder and pseudo-quotient from which Di is available, and the adder Ai having inputs from the associated correction register and the adder-residuator Ri to give the quotient Qi which is an input for the next unit including adder-residuator Ri 1 and adder Ai 1.
Claim 30
Dependent Claim
77 words
A device as claimed in claim 25, wherein there are provided m units including an adder-residuator and an adder corresponding to the m decimal digits, the adder-residuator Ri being arranged to give the remainder and pseudo-quotient from which Di is available, and the adder Ai having inputs from the associated correction register and the adder-residuator Ri to give the quotient Qi which is an input for the next unit including adder-residuator Ri 1 and adder Ai 1.
Claim 31
Dependent Claim
66 words
A device as claimed in claim 1 and also adapted to cover mixed numbers, wherein the whole number part is converted as stated and wherein the switching and programming means is adapted to switch inputs of the adder-residuator whereby multiplication of the fractional number part by 10 is obtainable, said main shift register having further bit positions Pn 3 and Pn 2 to receive multiplication overflow.
Claim 32
Dependent Claim
66 words
A device as claimed in claim 29 and also adapted to convert mixed numbers, wherein the whole number part is converted as stated and wherein the switching and programming means is adapted to switch inputs of the adder-residuator whereby multiplication of the fractional number part by 10 is obtainable, said main shift register having further bit positions Pn 3 and Pn 2 to receive multiplication overflow.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-02 | 1975-11-01 | 1976-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-02 | 1979-11-01 | 1980-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-02 | 1983-11-01 | 1984-05-02 | $7700.00 | Window Closed / Lapsed |