Dc-dc regulated inverter employing pulse-width modulation with a constant volt-second sensing transformer

Claim 2

A static inverter comprising a source of direct current line voltage, switching means; output transformer means, said transformer means comprising first and second core members, a primary winding wound common to each of said core members, a sensing winding wound about said second core member, an output winding wound common to each of said first and second core members, each of said core members having a square hysteresis characteristic with the permeability of said second core being appreciably less than that of said first core; said transformer primary, output, and sensing windings being comprised of a like number of turns, said first and second core members defining like mean magnetic path lengths, and said first and second core members having equal cross sectional areas whereby a constant volt-second product is established for the output waveform from said transformer output winding over a predetermined ratio of line voltage source magnitude; said switching means being adapted to periodically apply said line voltage source to said transformer primary winding for a predetermined period of time the duration of which is less than the time between the initiation of said periodic applications, said primary winding and said line voltage source establishing a magnetizing current in said primary winding sufficient to saturate said first core within the time period between successive applications of said line source to said primary winding and insufficient to effect saturation of said second core during this time period, switching control means connected to said sensing winding and responsive to the voltage induced therein to disable said switching means at the time of saturation of said first core member, and said switching signal source comprising a further static inverter employing a further saturable core output transformer the core of which comprises the same material as that of said output transformer first core member.

Claim 3

A static inverter as defined in claim 1 wherein said further saturable transformer core and said output transformer first core member are embodied in a common ambient temperature environment.

Claim 4

A static inverter comprising a source of direct current line voltage switching means; output transformer means, said transformer means comprising first and second core members, a primary winding wound common to each of said core members, a sensing winding wound about said second core member, an output winding wound common to each of said first and second core members, each of said core members having a square hysteresis characteristic with the permeability of said second core being appreciably less than that of said first core; said primary, output, and sensing windings being comprised of a like number of turns, said first and second core members defining like mean magnetic path lengths, and said First and second core members having equal cross sectional areas whereby a constant volt-second product is established for the output waveform from said transformer output winding over a predetermined ratio of line voltage source magnitude; said switching means comprising a source of alternating current square wave switching signal of predetermined frequency, transistor switching means receiving said switching signal and being rendered conductive thereby in synchronism with successive like half-cycle periods of said switching signal, said transistor means being serially connected with said line voltage source and said transformer primary winding and effecting a low impedance interconnection therebetween when conductive, the time duration of half-cycles of said switching signal being such as to effect saturation of said first core member prior to the termination of said half-cycles; and switching control means comprising means responsive to a predetermined level of the signal induced in said transformer sensing winding to render said transistor means non-conductive for the ensuing portion of said switching signal half-cycles, said switching control means comprising silicon controlled rectifier means responsive to said predetermined sense winding signal level to conduct and disable a base drive interconnection between said transistor means and said switching signal source.

Claim 5

A static inverter comprising a source of direct current line voltage switching means; output transformer means, said transformer means comprising first and second core members, a primary winding wound common to each of said core members, a sensing winding wound about said second core member, an output winding wound common to each of said first and second core members, each of said core members having a square hysteresis characteristic with the permeability of said second core being appreciably less than that of said first core; said primary, output, and sensing windings being comprised of a like number of turns, said first and second core members defining like mean magnetic path lengths, and said First and second core members having equal cross sectional areas whereby a constant volt-second product is established for the output waveform from said transformer output winding over a predetermined ratio of line voltage source magnitude; said switching means comprising a source of alternating current square wave switching signal of predetermined frequency, transistor switching means receiving said switching signal and being rendered conductive thereby in synchronism with successive like half-cycle periods of said switching signal, said transistor means being serially connected with said line voltage source and said transformer primary winding and effecting a low impedance interconnection therebetween when conductive, the time duration of half-cycles of said switching signal being such as to effect saturation of said first core member prior to the termination of said half-cycles; and switching control means comprising means responsive to a predetermined level of the signal induced in said transformer sensing winding to render said transistor means non-conductive for the ensuing portion of said switching signal half-cycles, said switching control means comprising silicon controlled rectifier means responsive to said predetermined sense winding signal level to conduct and disable a base drive interconnection between said transistor means and said switching signal source.

Claim 6

A static inverter as defined in claim 3 comprising zener diode means serially connected between said transformer sense winding and gating means associated with said silicon controlled rectifier means.

Claim 7

A static inverter as defined in claim 4 wherein said switching means is embodied as a further static inverter employing a further saturable core output transformer the core of which comprises the same material as that of said output transformer first core member.

Claim 8

A static inverter as defined in claim 5 wherein said further saturable transformer core and said output transformer first core member are embodied in a common ambient temperature environment.