Fail-safe duty cycle checking circuit

Claim 2

A fail-safe duty cycle checking circuit comprising a. an amplifying circuit means having a first and a second input and an output, said first input of said amplifying circuit means for receiving a square wave input signal of fixed peak to peak amplitude, said second input of said amplifying circuit for receiving a reference signal proportional to the duty cycle of said square wave input signal, b. a feedback loop connected between said output and said first input of said amplifying circuit means for providing an upper and a lower hysteresis level, said reference signal effective to shift said upper and said lower hysteresis levels upward whenever said duty cycle of said square wave input signal is greater than a predetermined duty cycle value and downward whenever said duty cycle of said square wave input signal is less than said predetermined duty cycle value, the raising and lowering of said upper and said lower hysteresis levels by said reference signal beyond preselected upper and lower values rendering said amplifying circuit means incapable of producing an output signal on said output of said amplifying circuit means and, c. a photosensitive means having a radiant energy soUrce connected in said feedback loop for monitoring the condition thereof and having a photoresistive element connected to said first and said second inputs of said amplifying circuit means and responsive to said radiant energy source, and photoresistive element assuming a high impedance whenever said radiant energy source emits no radiant energy due to a component failure in said feedback loop to thereby render any square wave input signal incapable of causing an output from said amplifying circuit means during a component failure in said feedback loop.

Claim 3

The fail-safe duty cycle checking circuit as defined in claim 1, wherein said amplifying circuit means includes a differential amplifier means having a first and a second input and an output, said feedback loop being connected between said output and said first input of said differential amplifier means, said photoresistive element being connected to said first and said second input of said differential amplifier means.

Claim 4

a switching stage including a third transistor device having an emitter electrode, a collector electrode, and a base electrode, said base electrode of said third transistor device directly connected to the junction of said first and second resistive elements, said emitter electrode of said third transistor device connected directly to said first positive potential, said collector electrode of said third transistor electrically connected to a second reference voltage potential which is more positive than said first reference voltage potential and is the level of the lower peak of said fixed peak to peak amplitude square wave, and

Claim 5

a switching stage including a third transistor device having an emitter electrode, a collector electrode, and a base electrode, said base electrode of said third transistor device directly connected to the junction of said first and second resistive elements, said emitter electrode of said third transistor device connected directly to said first positive potential, said collector electrode of said third transistor electrically connected to a second reference voltage potential which is more positive than said first reference voltage potential and is the level of the lower peak of said fixed peak to peak amplitude square wave, and

Claim 6

a low impedance output stage including a fourth transistor device having an emitter electrode, a collector electrode, and a base electrode, said base electrode of said fourth transistor device electrically connected to said collector electrode of said third transistor device through a fifth resistive element, said collector electrode of said fourth transistor device directly connected to said first positive voltage potential, said emitter electrode of said fourth transistor device connected to said first reference voltage potential through series connected sixth and seventh resistive elements, said output of said amplifying circuit means taken from the junction of said sixth and seventh resistive elements, d. a feedback loop connected between said output of said amplifier circuit means and said positive input of said differential amplifier stage for providing an upper and a lower hysteresis level, said time averaging means output effective to shift said upper and lower hysteresis levels upward whenever said duty cycle of said fixed peak to peak amplitude square wave is greater than a predetermined duty cycle value and downward whenever said duty cycle of said fixed peak to peak amplitude square wave is less than said predetermined duty cycle value, and e. a photosensitive means having a radiant energy source connected in said feedback loop for monitoring the condition thereof and having a photoresistive element connected to said input of said first stage of said cascaded amplifying means and responsive to said radiant energy source, said photoresistive element assuming a high impedance condition whenever said radiant energy source emits no energy to thereby render any square wave input signal incapable of causing an output from said amplifying circuit means during a component failure in said feedback loop.

Claim 7

a low impedance output stage including a fourth transistor device having an emitter electrode, a collector electrode, and a base electrode, said base electrode of said fourth transistor device electrically connected to said collector electrode of said third transistor device through a fifth resistive element, said collector electrode of said fourth transistor device directly connected to said first positive voltage potential, said emitter electrode of said fourth transistor device connected to said first reference voltage potential through series connected sixth and seventh resistive elements, said output of said amplifying circuit means taken from the junction of said sixth and seventh resistive elements, d. a feedback loop connected between said output of said amplifier circuit means and said positive input of said differential amplifier stage for providing an upper and a lower hysteresis level, said time averaging means output effective to shift said upper and lower hysteresis levels upward whenever said duty cycle of said fixed peak to peak amplitude square wave is greater than a predetermined duty cycle value and downward whenever said duty cycle of said fixed peak to peak amplitude square wave is less than said predetermined duty cycle value, and e. a photosensitive means having a radiant energy source connected in said feedback loop for monitoring the condition thereof and having a photoresistive element connected to said input of said first stage of said cascaded amplifying means and responsive to said radiant energy source, said photoresistive element assuming a high impedance condition whenever said radiant energy source emits no energy to thereby render any square wave input signal incapable of causing an output from said amplifying circuit means during a component failure in said feedback loop.

Claim 8

The fail-safe duty cycle checking circuit as defined in claim 1, wherein said reference signal is a time average of said square wave input signal.

Claim 9

The fail-safe duty cycle checking circuit as defined in claim 1, wherein said feedback loop provides regenerative feedback to said first input of said amplifying circuit means.

Claim 10

The fail-safe duty cycle checking circuit as defined in claim 1, wherein said radiant energy source comprises a light bulb.

Claim 11

The fail-safe duty cycle checking circuit as defined in claim 1, wherein said photoresistive element comprises a photopositive resistor.

Claim 12

The fail-safe duty cycle checking circuit as defined in claim 1, wherein a cascaded amplifying circuit is interposed between said photoresistive means and said first input of said amplifier circuit means.

Claim 13

The fail-safe duty cycle checking circuit as defined in claim 7, wherein a current-limiting resistor electrically couples said cascaded amplifying means to said amplifying circuit means.

Claim 14

The fail-safe duty cycle checking circuit as defined in claim 8, wherein said upper and lower hysteresis levels are proportional to the ratio of the impedance of said feedback loop and the impedance of said current limiting resistor.

Claim 15

The fail-safe duty cycle checking circuit as defined in claim 7, wherein said cascaded amplifying circuit comprises first and second stages, said first stage being a common emitter amplifying means having an input connected to said photoresistive element and producing an output which is a square wave signal of fixed peak to peak amplitude, said second stage comprising an emitter follower amplifying means having an input connected to said output of said common emitter amplifying means and attenuating said output of said common emitter amplifying means, and an output of less than unity gain connected to said first input of said amplifying circuit means.

Claim 16

The fail-safe duty cycle checking circuit as defined in claim 10, wherein a Zener diode and a fuse are interconnected in said first stage of said cascaded amplifying circuit for ensuring a constant peak to peak amplitude at said output of said first stage of said cascaded amplifying circuit, as well as at said output of said amplifier circuit means, said constant peak to peak amplitude unable to increase in value since failure of said Zener diode causes said fuse to open-circuit rendering said fail-safe duty cycle checking circuit inoperable.

Claim 17

The fail-safe duty cycle checking circuit as defined in claim 10, wherein a time averaging means is connected to said square wave signal output of said common emitter amplifying means to provide an output which is a time average of said square wave signal output of said common emitter amplifying means and which is connected as said second input to said amplifying circuit means.

Claim 18

The fail-safe duty cycle checking circuit as defined in claim 1, wherein said upper and lower hysteresis levels are equally displaced from a level which is the time average of said sqUare wave input signal.

Claim 19

A fail-safe duty cycle checking circuit comprising a. a cascaded amplifying circuit having a first and a second stage, each having an input and an output, said first stage input connected for receiving a square wave input signal, said first stage fixing the peak to peak amplitude of said square wave input signal and said fixed peak to peak amplitude square wave appearing on said first stage output and delivered to said second stage input, said second stage attenuating and centering said fixed peak to peak amplitude square wave, the attenuated square wave produced on said second stage output, b. time averaging means having an input connected to said output of said first stage of said cascaded amplifying circuit and an output which is proportional to the duty cycle of said fixed peak to peak amplitude square wave, c. an amplifying circuit means having a first and a second input and an output, said first input of said amplifying circuit means electrically connected to said output of said second stage of said cascaded amplifying circuit, said second input of said amplifying circuit electrically connected to said output of said time averaging means, said amplifying circuit means comprising

Claim 20

A fail-safe duty cycle checking circuit comprising a. a cascaded amplifying circuit having a first and a second stage, each having an input and an output, said first stage input connected for receiving a square wave input signal, said first stage fixing the peak to peak amplitude of said square wave input signal and said fixed peak to peak amplitude square wave appearing on said first stage output and delivered to said second stage input, said second stage attenuating and centering said fixed peak to peak amplitude square wave, the attenuated square wave produced on said second stage output, b. time averaging means having an input connected to said output of said first stage of said cascaded amplifying circuit and an output which is proportional to the duty cycle of said fixed peak to peak amplitude square wave, c. an amplifying circuit means having a first and a second input and an output, said first input of said amplifying circuit means electrically connected to said output of said second stage of said cascaded amplifying circuit, said second input of said amplifying circuit electrically connected to said output of said time averaging means, said amplifying circuit means comprising

Claim 21

The fail-safe duty cycle checking circuit as defined in claim 14, wherein said feedback loop provides regenerative feedback to said first input of said amplifying circuit means.

Claim 22

The fail-safe duty cycle checking circuit as defined in claim 14, wherein said radiant energy source comprises a light bulb.

Claim 23

The fail-safe duty cycle checking circuit as defined in claim 14, wherein said photoresistive element comprises a photopositive resistor.

Claim 24

The fail-safe duty cycle checking circuit as defined in claim 14, wherein said upper and lower hysteresis levels are equally displaced from a level which is the time average of said square wave input signal.

Claim 25

The fail-safe duty cycle checking circuit as defined in claim 14, wherein a current-limiting resistor electrically couples said cascaded amplifying means to said amplifying circuit means.

Claim 26

The fail-safe duty cycle checking circuit as defined in claim 19, wherein said upper and lower hysteresis levels are proportional to the ratio of the impedance of said feedback loop and the impedance of said current limiting resistor.