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US3660171A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing semiconductor device utilizing ion implantation

Assignee: Hitachi Ltd
•
Filing: 1969-12-24
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Granted: 1972-05-02
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Expires: 1989-12-24
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Abstract

Abstract A method for producing a transistor structure utilizing ion implantation, comprising the steps of implanting ions of baseforming impurity into a predetermined portion of a surface of a semiconductor body serving as a collector and heated to a temperature above 600* C. but below the melting point of the semiconductor to form a base region, and thereafter implanting ions of emitter-forming impurity into a predetermined portion of the surface of said base region heated to a temperature in the range of 400* to 600* C. to form an emitter region.

Inventors

  • 👤 Takashi Tsuchimoto
  • 👤 Takashi Tokuyama
  • 👤 Kiichi Komatsubara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 04:13
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10D; H10D99/00; H10P95/00

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 35 words
A method according to claim 1, wherein said first temperature is above 600* C. but below the melting point of the semiconductor and said second temperature is in the range of 400* to 600* C.
Claim 2
Independent Claim 184 words
A method for producing a planar type transistor comprising the steps of: a. forming a mask layer having an opening on a surface of a silicon body of a first conductivity type; b. bombarding an ion beam of a first active impurity onto the surface of the silicon body heated at a temperature between 600* C. and the melting point of silicon through said mask layer to form a base region in the surface of the silicon body; c. forming another mask layer having an opening smaller than said opening on said mask layer and said silicon body; d. bombarding an ion beam of a second active impurity onto the surface of said silicon body heated to a temperature of 400* to 600* C. to form an emitter region in said base region; e. removing the mask layers from the surface of the silicon body; f. forming a passivation film on the surface of the silicon body; g. forming openings in the passivation film to expose electrode portions of the silicon body; and h. connecting electrodes to the electrode portions of the silicon body.

References Cited (Backward Citations)

US3390019A Cited
US3404451A Cited
US3457632A Cited
US3533857A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-02 1975-11-01 1976-05-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-02 1979-11-01 1980-05-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-02 1983-11-01 1984-05-02 $7700.00 Window Closed / Lapsed

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