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US3660157A Expired / Lapsed US ⏱️ 0.0 years remaining

Enhanced contrast semiconductor wafer alignment target

Assignee: Applied Materials Inc
•
Filing: 1969-08-18
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Granted: 1972-05-02
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Expires: 1989-08-18
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Abstract

Abstract An enhanced contrast semiconductor wafer alignment target for use in automatic, light balanced, null seeking, servocontrolled mask-to-wafer aligners. The target has a line border which differs sharply in its light reflecting characteristic from the surrounding surface of the semiconductor wafer. Within the target area defined by the line border are a plurality of light reflecting and light removing areas arranged, preferably, in alternating sequence to form a checkerboard or parallel line pattern. For semiconductor wafers in which the target cannot be formed in an overlying, electrically insulative layer because of the subsequent removal of the layer, the target is etched directly into the semiconductor materials.

Inventors

  • 👤 Philippe Villers
  • 👤 Martin A Allen
  • 👤 James M Mulvaney

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 16:53
CPC Classifications
H; H10; H10P; H10P95/00; G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24628

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 27 words
The target pattern area of claim 1 further characterized by said line boundary comprising a surface of said semiconductor material which sloped downwardly from said specular surface.
Claim 2
Dependent Claim 50 words
The target pattern area of claim 1 further characterized by said plurality of light reflecting and light removing areas comprising a plurality of intersecting valleys profiled into the semiconductor material, said valleys having upwardly sloping sides which meet the unprofiled specular surface of the semiconductor material within the target area.
Claim 3
Dependent Claim 57 words
The target pattern area of claim 1 further characterized by said plurality of light reflecting and light removing areas comprising a plurality of parallel valleys profiled into the semiconductor material at right angles to said line boundary, said valleys having upwardly sloping sides which meet the unprofiled specular surface of the semiconductor material within the target area.
Claim 4
Dependent Claim 47 words
The apparatus of claim 1 further characterized by said semiconductor wafer having a layer of transparent material positioned above the specular surface of the wafer and wherein said target pattern area line boundary comprises a surface of said transparent material which slopes upwardly from said specular surface.

References Cited (Backward Citations)

US2944321A Cited
US3468728A Cited
US3486953A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-02 1975-11-01 1976-05-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-02 1979-11-01 1980-05-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-02 1983-11-01 1984-05-02 $7700.00 Window Closed / Lapsed

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