Analog convertor and computer circuit producing optimized pulse output

Claim 2

An analog-to-digital converter of the type having an analog signal integrator, a threshold detector responsive to the crossing of a selected threshold level by said integrator output, a clock, switching means responsive to the outputs of said threshold detector and said clock, and means for applying a feedback input to said integrator for opposing and overcoming an analog signal input to said integrator, said switching means being arranged to turn said feedback input on and off so that said integrator output is a ramp sloping in alternate directions during alternate time periods; wherein: said switching means comprises at least one logic level input and one clocked input, and is arranged to switch said feedback input whenever a net change of logic level at said one input is followed by receipt of a clocking signal at said other input, but does not switch said feedback input if no net change in logic level occurs at said one input between the receipt of two consecutive clocking signals at said other input; said clocking input of said switching means is operatively connected to said threshold detector output; whereby said switching means switches said feedback input upon the occurrence of the next clock-generated input thereto following a net crossing of said threshold level by said integrator output ramp, said switching means always being fully synchronous with said clocking signal.

Claim 3

The device of claim 1 wherein said switching means comprises: a feedback control switch; a gate having a pair of inputs, said gate being connected to open and close said feedback control switch; a flip-flop having an output connected to control one of said gate inputs; frequency dividing means connected to receive said clock output and divide it to a lower repetition rate, and to segregate alternate intervals of the higher repetition rate clock output; the lower repetition rate output of said frequency divider means being connected to control said trigger input; the other one of said gate inputs being energized by said frequency dividing means during alternate clock intervals; said gate opening said feedback control switch only upon coincidence of one of said flip-flop states with alternate clock intervals.

Claim 4

The device of claim 2, further comprising: means for adjusting the level of said feedback input.

Claim 5

The device of claim 2 wherein: said frequency dividing and interval segregating means is a second flip-flop, and the frequency division ratio thereof equals two.

Claim 6

The device of claim 4 wherein: said two flip-flops are both incorporated within a single integrated circuit confined to a single package.

Claim 7

The device of claim 4 wherein: said two flip-flops are JK circuits.

Claim 8

The device of claim 1 wherein: said threshold detector is an operational amplifier which is driven to positive or negative saturation, depending upon the instantaneous polarity of said integrator output relative to said selected threshold level.

Claim 9

The device of claim 1 wherein: said integrator comprises an operational amplifier and a capacitor connected thereacross to provide negative feedback; said operational amplifier and said feedback capacitor are both incorporated within a single integrated circuit confined to a single package.

Claim 10

The device of claim 1 further comprising: input means for applying an additional variable analog signal to said feedback applying means instead of a feedback input, whereby the average value of the net input to said integrator represents the average value of said first-mentioned analog signal divided by the average value of said additional variable signal at said additional input means.

Claim 11

The device of claim 1 further comprising: dual input means to said integrator including an analog switch having a pair of input electrodes and an output electrode connected to the input of said integrator and arranged so that the average value of the net signal input to said integrator represents the product of the average values of said inputs to said analog switch.

Claim 12

An analog-to-digital converter which optimizes its output relative to a quantized time domain comprising discrete equal time intervals; comprising: integrator means for computing the integral of an analog signal; time-partitioning means; means for progressively overcoming the effect of said analog signal input on said integrator; means responsive to said integral computing means for determining whether the integral of said analog signal is above or below a selected level; and switching means responsive to said determining means and said time-partitioning means, and arranged to allow said overcoming means to overcome the effect of said analog signal on said integrator to a predetermined extent during at least a portion of time intervals when said integral is above said selected level upon the occurrence of a time-partitioning event, and to reduce the effectiveness of said overcoming means in overcoming the effect of said analog signal on said integrator below said predetermined extent at least during those time intervals when said integral is below said selected level upon the occurrence of a time-partitioning event, whereby said switching means is always fully synchronous with said time-partitioning event.

Claim 13

An analog-to-digital converter which optimizes its output relative to a quantized time domain comprising discrete equal time intervals; comprising: integrator means for computing the integral of an analog signal; time-partitioning means; means for progressively overcoming the effect of said analog signal input on said integrator; means responsive to said integral computing means for determining whether the integral of said analog signal is above or below a selected level; and switching means responsive to said determining means and said time-partitioning means, and arranged to allow said overcoming means to overcome the effect of said analog signal on said integrator to a predetermined extent during at least a portion of time intervals when said integral is above said selected level upon the occurrence of a time-partitioning event, and to reduce the effectiveness of said overcoming means in overcoming the effect of said analog signal on said integrator below said predetermined extent at least during those time intervals when said integral is below said selected level upon the occurrence of a time-partitioning event, whereby said switching means is always fully synchronous with said time-partitioning event.

Claim 14

A device as in claim 11 wherein said switching means comprises: means responsive to said time-partitioning means for generating one or another of the values of a plural-valued quantity following time-partitioning events and responsive to said determining means to generate one of said values when said integral is above said selected level and another of said values when said integral is below said selected level; and disabling means responsive to said plural-valued quantity generator to disable said overcoming means when one of said values of said plural valued quantity is generated.

Claim 15

A device as in claim 12 wherein: said time-partitioning means includes a times base, and a dividing means for partitioning time at a rate which is a sub-multiple of the repetition rate of said time base; said plural-valued quantity generator makes its value decisions at said sub-multiple rate tiMe-partitioning events; said analog-to-digital converter device further comprises means for detecting coincidence between said first state of said plural-valued quantity generator and alternate intervals of time as partitioned by said higher rate time base; and said disabling means is arranged to make said overcoming means effecting during intervals when said coincidence is detected, and to disable said overcoming means during all other intervals.

Claim 16

A circuit comprising: an analog-to-digital converter of the type producing a pulse train output which is optimized relative to a quantized time domain and the average value of which is an analog representation of the input signal to said converter; means for applying to said analog-to-digital converter an input signal which is an analog representation of the flow rate of a sample of expired air; a first analog integrator for integrating the output of said converter; means for detecting when the output of said first analog integrator reaches a selected stop threshold level; a digital time base generator; a digital counter; means including a gate connecting the output of said time base generator to the input of said digital counter; means for first opening said gate to the passage of said time base generator output, and subsequently closing said gate when the output of said first analog integrator reaches said selected stop threshold level; means including a digital-to-analog converter receiving the output of said counter and converting the cumulative count thereof to an analog signal representing the open time of said gate; and a reciprocating circuit including a second analog integrator, a constant reference level applied to the input of said second analog signal integrator, said constant reference level being opposite in polarity to, and exceeding the amplitude of, said time-representing analog signal, a threshold detector responsive to the crossing of a selected threshold level by said second analog integrator output, means for receiving a clocking signal, switching means of the type which has at least one logic level input and one clocked input and which changes its state whenever a net change of logic level at said one input is followed by a clocking signal at said other input but does not change its state if no net change in logic level occurs at said one input between the receipt of two consecutive clocking signals at said other input, said clocked input being connected at least indirectly to said clocking signal means, said logic level input being connected at least indirectly to said threshold detector output, said switching means being arranged for turning on and off a feedback input to said second analog integrator depending upon the sate of said switching means; said time-representing analog signal output being connected to said switching means for use as said feedback input to said second analog integrator whereby said circuit computes the reciprocal of said gate-open time; and means for displaying the output of said reciprocating circuit as a maximum expiratory flow rate quantity.

Claim 17

A circuit comprising: an analog-to-digital converter of the type producing a pulse train output which is optimized relative to a quantized time domain and the average value of which is an analog representation of the input signal to said converter; means for applying to said analog-to-digital converter an input signal which is an analog representation of the flow rate of a sample of expired air; a first analog integrator for integrating the output of said converter; means for detecting when the output of said first analog integrator reaches a selected stop threshold level; a digital time base generator; a digital counter; means including a gate connecting the output of said time base generator to the input of said digital counter; means for first opening said gate to the passage of said time base generator output, and subsequently closing said gate when the output of said first analog integrator reaches said selected stop threshold level; means including a digital-to-analog converter receiving the output of said counter and converting the cumulative count thereof to an analog signal representing the open time of said gate; and a reciprocating circuit including a second analog integrator, a constant reference level applied to the input of said second analog signal integrator, said constant reference level being opposite in polarity to, and exceeding the amplitude of, said time-representing analog signal, a threshold detector responsive to the crossing of a selected threshold level by said second analog integrator output, means for receiving a clocking signal, switching means of the type which has at least one logic level input and one clocked input and which changes its state whenever a net change of logic level at said one input is followed by a clocking signal at said other input but does not change its state if no net change in logic level occurs at said one input between the receipt of two consecutive clocking signals at said other input, said clocked input being connected at least indirectly to said clocking signal means, said logic level input being connected at least indirectly to said threshold detector output, said switching means being arranged for turning on and off a feedback input to said second analog integrator depending upon the sate of said switching means; said time-representing analog signal output being connected to said switching means for use as said feedback input to said second analog integrator whereby said circuit computes the reciprocal of said gate-open time; and means for displaying the output of said reciprocating circuit as a maximum expiratory flow rate quantity.

Claim 18

A device as in claim 14 wherein said gate opening means comprises; means for detecting when the output of said first analog integrator reaches a selected start threshold level; and means for opening said gate upon the attainment of said start threshold level.

Claim 19

An analog-to-digital data conversion method comprising the steps of a. providing an analog data signal having a variable characteristic as an input to a feedback loop, b. providing a digital pulse train sequence within said feedback loop in response to said variable analog signal, and c. optimizing said digital pulse train sequence by processing said variable analog data signal input and said digital pulse train signal within said feedback loop in accordance with the expression where n is a variable integer, a represents a seQuence which is a function of said pulse train sequence having a maximum value amax and a minimum value amin,where a (a0, a1, a2, . . . a1, . . . an 1) x(t) represents said variable analog signal, tn represents an arbitrary clock time, and an represents a value of said sequence which is a function of said pulse sequence at tn, said an value being amax when is above a predetermined value and said an value being amin when is below said predetermined value, whereby said digital pulse train is optimized relative to a quantized time domain comprising discrete equal time intervals so as to provide a clocked optimal digital pulse train sequence representation of said variable analog signal as an output from said feedback loop.

Claim 20

An analog-to-digital data conversion method comprising the steps of a. providing an analog data signal having a variable characteristic as an input to a feedback loop, b. providing a digital pulse train sequence within said feedback loop in response to said variable analog signal, and c. optimizing said digital pulse train sequence by processing said variable analog data signal input and said digital pulse train signal within said feedback loop in accordance with the expression where n is a variable integer, a represents a seQuence which is a function of said pulse train sequence having a maximum value amax and a minimum value amin,where a (a0, a1, a2, . . . a1, . . . an 1) x(t) represents said variable analog signal, tn represents an arbitrary clock time, and an represents a value of said sequence which is a function of said pulse sequence at tn, said an value being amax when is above a predetermined value and said an value being amin when is below said predetermined value, whereby said digital pulse train is optimized relative to a quantized time domain comprising discrete equal time intervals so as to provide a clocked optimal digital pulse train sequence representation of said variable analog signal as an output from said feedback loop.

Claim 21

In a measuring device in which at least a pair of variable analog signals are introduced in order to determine a measured quantity, wherein a system delay relative to said other analog signal is introduced in one of said analog signals during production of said one analog signal, the improvement comprising an analog to digital conversion means having a feedback loop system in which a digital pulse train sequence representation of said other variable analog signal is produced, said feedback system including means for optimizing said pulse train sequence by processing said sequence in accordance with the expression where n is a variable integer, a represents a sequence which is a function of said pulse train sequence having a maximum value amax and a minimum value amin, where a (a0, a1, a2, . . . ai, . . . an 1), x(t) represents said other variable analog signal, tn represents an arbitrary clock time, and an represents a value of said sequence which is a function of said pulse sequence at tn, said an value being amax when is above a predetermined value and said an value being amin when is below said predetermined value, so as to provide an optimal pulse train sequence representation of said other variable analog signal as an output of said conversion means; and a digital delay line for introducing a time delay in said optimized pulse train output which is substantially equivalent to said system delay, said digital delay line including a clocked shift register operatively connected to said conversion means to receive and repeatedly shift said optimized pulse train output, whereby said analog signals are effectively synchronized during said determination

Claim 22

In a measuring device in which at least a pair of variable analog signals are introduced in order to determine a measured quantity, wherein a system delay relative to said other analog signal is introduced in one of said analog signals during production of said one analog signal, the improvement comprising an analog to digital conversion means having a feedback loop system in which a digital pulse train sequence representation of said other variable analog signal is produced, said feedback system including means for optimizing said pulse train sequence by processing said sequence in accordance with the expression where n is a variable integer, a represents a sequence which is a function of said pulse train sequence having a maximum value amax and a minimum value amin, where a (a0, a1, a2, . . . ai, . . . an 1), x(t) represents said other variable analog signal, tn represents an arbitrary clock time, and an represents a value of said sequence which is a function of said pulse sequence at tn, said an value being amax when is above a predetermined value and said an value being amin when is below said predetermined value, so as to provide an optimal pulse train sequence representation of said other variable analog signal as an output of said conversion means; and a digital delay line for introducing a time delay in said optimized pulse train output which is substantially equivalent to said system delay, said digital delay line including a clocked shift register operatively connected to said conversion means to receive and repeatedly shift said optimized pulse train output, whereby said analog signals are effectively synchronized during said determination

Claim 23

A device as in claim 17 for use as a lung function analyzer, further comprising: means for applying an input signal to said conversion means which is an analog representation of the volumetric flow rate of a moving sample of expired air, said input signal being said other analog signal; means for analyzing the nitrogen concentration within said expired air sample, and generating a substantially linear analog representation of said concentration, said means introducing a time delay into the production of said analog representation which is substantially equal to the delay time of said digital delay line, said analog representation of said concentration being said one analog signal, said analyzing means introduced time delay being said system delay; a second pulse-train-producing circuit, the output of which represents a quantity in an optimal manner relative to a quantized time domain; means for multiplying the output of said delay line and the output of said linear nitrogen concentration signal generator, and applying the product thereof to the input of said second pulse-trAin-producing circuit, whereby the output pulse train thereof represents the product of said inputs; and means for reading out said product as the total nitrogen wash-out in said sample of expired air.

Claim 24

A device as in claim 17, further comprising: a clocked coincidence gate connected to receive the output of said shift register; and means operatively connected to said shift register and to said coincidence gate to provide a clock signal thereto, whereby said coincidence gate restores clock synchronization to said pulse train output of said shift register.