US3659226A
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Digital frequency modulator
Assignee: Italtel SpA
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Filing: 1970-05-11
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Granted: 1972-04-25
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Expires: 1990-05-11
Abstract
Abstract Two pulse trains with harmonically related repetition frequencies 1/To, 1/nTo are derived from an original square wave of cadence 2/To, the pulses of each train having the width To/4 of the square-wave pulses. With the aid of a second square wave of cadence To, produced by frequency halving from the original square wave, the two harmonically related pulse trains are additively or subtractively combined so as to produce an irregular pulse sequence with n + OR - 1 pulses in each period nTo of the lower-frequency train. A digital pulse counter derives from this irregular pulse sequency a low-frequency square wave converted, by filtration, into its fundamental sine wave whose frequency can thus be selectively varied, with only minor phase discontinuities, between three predetermined values related to one another as (n+1) : n : (n-1). In an alternative embodiment, the keying frequencies are related to the basic frequency as (2n+1) : 2n : (2n-1). The two pulse trains are generated by progressive frequency division, starting with the original square wave, and selective gating.
Inventors
- 👤 Emanuele Angeleri
- 👤 Fabio Balugani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:23
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/12; H04L27/122; H03; H03K; H03K3/00; H03K3/64; H03K3/72
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
131 words
A digital frequency modulator comprising a source of equispaced pulses constituting a basic pulse train; logical circuitry for superimposing upon said basic pulse train a modulating pulse train with a cadence subharmonically related to the cadence of said basic pulse train, thereby producing a modified pulse sequence with a number of pulses per unit of time algebraically related to the cadences of said basic and modulating pulse trains; a step-down circuit with a multiplicity of cascaded binary stages connected to receive said pulse sequence from said logical circuitry for converting same into an output square wave with a mean frequency lower than the cadence of said modulating pulse train, said frequency being determined by said number of pulses; and input means for selectively activating said logical circuitry to vary said frequency.
Claim 2
Dependent Claim
131 words
A digital frequency modulator comprising a source of equispaced pulses constituting a basic pulse train; logical circuitry for superimposing upon said basic pulse train a modulating pulse train with a cadence subharmonically related to the cadence of said basic pulse train, thereby producing a modified pulse sequence with a number of pulses per unit of time algebraically related to the cadences of said basic and modulating pulse trains; a step-down circuit with a multiplicity of cascaded binary stages connected to receive said pulse sequence from said logical circuitry for converting same into an output square wave with a mean frequency lower than the cadence of said modulating pulse train, said frequency being determined by said number of pulses; and input means for selectively activating said logical circuitry to vary said frequency.
Claim 3
Dependent Claim
19 words
A frequency modulator as defined in claim 1, further comprising bistable means periodically triggerable by said step down circuit.
Claim 4
Dependent Claim
23 words
A frequency modulator as defined in claim 1 further comprising filter means for isolating a fundamental sine wave from said output square wave.
Claim 5
Dependent Claim
106 words
A frequency modulator as defined in claim 1 wherein said source comprises oscillator means for generating an original square wave and multistage frequency-dividing means driven by said oscillator means for producing said basic pulse train as a regular succession of pulses with a cadence subharmonically related to the frequency of said original square wave, said logical circuitry including coincidence means connected to different stages of said frequency-dividing means for creating said modulating pulse train as a series of keying pulses with a pulse width substantially smaller than half their recurrence period and ranging between one and three times the pulse width of said basic pulse train.
Claim 6
Dependent Claim
151 words
A frequency modulator as defined in claim 4 wherein said frequency-dividing means includes a first stage for deriving from said original square wave a second square wave of half the frequency of the former, said oscillator means and said first stage being connected to energize said coincidence means for producing said basic pulse train with a pulse width equal to that of said original square wave and with a cadence equaling four times the frequency of said square wave, said keying pulses having a width equaling the repetition period of said basic pulse train and a recurrence period equal to a multiple of said - train and a recurrence period equal to a multiple of repetition period, said coincidence means being connected to superimpose said keying pulses upon the output of said first stage in phased relationship to alter the number of pulses per recurrence period in said basic pulse train.
Claim 7
Dependent Claim
41 words
A frequency modulator as defined in claim 5 wherein said logical circuitry includes phase-inverting means for said keying pulses, said input means comprising signaling means for selectively operating said phase-inverting means whereby said number of pulses is alternately reduced and increased.
Claim 8
Dependent Claim
107 words
A frequency modulator as defined in claim 4 wherein said oscillator means comprises a square-wave generator of frequency 2/To, said frequency-dividing means including a plurality of cascaded binary dividers and flip-flop means in parallel therewith, said coincidence means comprising a first gate circuit for forming logical products of the outputs of several of said dividers to generate said series of keying pulses of pulse width To/2 and recurrence period 2kTo where k is an integer, and a second gate circuit for superimposing said keYing pulses upon the output of said flip-flop means, the latter output being a square wave of frequency 1/2 To and pulse width To/2.
Claim 9
Dependent Claim
86 words
A frequency modulator as defined in claim 7 wherein said flip-flop means is provided with a blocking circuit connected to said first gate circuit for preventing a switching of said flip-flop means in response to the output of said generator in the presence of a keying pulse, said second gate circuit comprising gate means connected to form the logical sum of said keying pulses and the outputs of said flip-flop means and said generator, thereby giving rise to an irregular succession of pulses of width To/4.
Claim 10
Dependent Claim
47 words
A frequency modulator as defined in claim 8 wherein said second gate circuit includes inversion means for selectively reversing the phase of said keying pulses with reference to said outputs of said flip-flop means and said generator, thereby varying the mean pulse cadence in said irregular succession.
Claim 11
Dependent Claim
55 words
A frequency modulator as defined in claim 7 wherein said first gate circuit comprises a plurality of AND gates for producing several series of keying pulses, said AND gates being partly provided with inverting inputs connected to stagger the keying pulses of different series, with progressively higher values of K, by a pulse width To/2.
References Cited (Backward Citations)
US2994790A
Cited
US3426296A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-25 | 1975-10-25 | 1976-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-25 | 1979-10-25 | 1980-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-25 | 1983-10-25 | 1984-04-25 | $7700.00 | Window Closed / Lapsed |