US3659209A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Slope polarity detector circuit
Assignee: General Electric Co
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Filing: 1969-09-29
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Granted: 1972-04-25
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Expires: 1989-09-29
Abstract
Abstract An electrical circuit for determining the polarity of the slope of an analog type voltage waveform includes a voltage comparator and time delay network providing a time delay of less than 0.05 times the period of one cycle of the voltage waveform being monitored. In a positive slope detector circuit, the analog input signal is supplied to the positive input terminal of the comparator and is also supplied through the time delay network to the negative input terminal. In a negative slope detector circuit, the time delay network is connected to the positive input terminal. A circuit including both the positive and negative slope detector circuits, and a logic gate connected to the outputs of the detector circuits, provides the function of a zero slope detector.
Inventors
- 👤 Charles Mcdonald Puckette
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:38
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; G; G01; G01R; G01R19/00; G01R19/12; G01R29/00; G01R29/02; H03; H03K; H03K5/00; H03K5/153; H03K5/1532
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
223 words
An electrical circuit for detecting the slope polarity of an analog input voltage waveform comprising a first differential voltage comparator provided with first positive and first negative inputs, said first positive input adapted to be supplied with an analog input voltage signal, said first negative input including a first electrical fixed time delay network continuously providing a sufficiently small fixed time delay Delta such that omega Delta is less than 1.0 where omega is the frequency of the analog input signal in radians per second, said first fixed time delay network is comprised of elements having particular values of resistance and reactance to provide a fixed time delay less than 0.05 times the period of one cycle of the input signal, said first negative input adapted to be continuously supplied with the analog input voltage signal in substantially undistorted form and merely being delayed by the time delay Delta from the undelayed signal applied to said first positive input upon passage through said first time delay network whereby said first comparator provides a continuous comparison of the amplitudes of the undelayed and delayed analog input voltage signal, the output of said first comparator being a binary logic voltage signal wherein the high state thereof corresponds to the time of positive polarity of the slope of the waveform of the analog input voltage signal.
Claim 2
Dependent Claim
223 words
An electrical circuit for detecting the slope polarity of an analog input voltage waveform comprising a first differential voltage comparator provided with first positive and first negative inputs, said first positive input adapted to be supplied with an analog input voltage signal, said first negative input including a first electrical fixed time delay network continuously providing a sufficiently small fixed time delay Delta such that omega Delta is less than 1.0 where omega is the frequency of the analog input signal in radians per second, said first fixed time delay network is comprised of elements having particular values of resistance and reactance to provide a fixed time delay less than 0.05 times the period of one cycle of the input signal, said first negative input adapted to be continuously supplied with the analog input voltage signal in substantially undistorted form and merely being delayed by the time delay Delta from the undelayed signal applied to said first positive input upon passage through said first time delay network whereby said first comparator provides a continuous comparison of the amplitudes of the undelayed and delayed analog input voltage signal, the output of said first comparator being a binary logic voltage signal wherein the high state thereof corresponds to the time of positive polarity of the slope of the waveform of the analog input voltage signal.
Claim 3
Dependent Claim
64 words
The electrical circuit set forth in claim 1 wherein said first time delay network comprises a first series resistor having a resistance value R and a reactive element, and said first positive input includes a second series resistor having an equal resistance value R to compensate for slight attenuation in amplitude of the input signal in its passage through said first time delay network.
Claim 4
Dependent Claim
27 words
The electrical circuit set forth in claim 2 wherein said reactive element is a capacitor and said first time delay network comprises a single section resistor-capacitor network.
Claim 5
Dependent Claim
35 words
The electrical circuit set forth in claim 3 wherein said capacitor is connected between ground and a juncture interconnecting one end of said first series resistor with said first negative input of said first comparator.
Claim 6
Dependent Claim
54 words
The electrical circuit set forth in claim 4 and further comprising a small capacitance capacitor connected between ground and a juncture interconnecting one end of said second series resistor with said first positive input of said first comparator for bypassing high frequency switching transients generated by said first comparator during changes of state thereof.
Claim 7
Dependent Claim
226 words
The electrical circuit set forth in claim 1 and further comprising a second differential voltage comparator provided with second positive and second negative inputs, said second negative input adapted to be supplied with the analog input voltage signal, said second positive input including a second fixed time delay network providing a sufficiently small and equal fixed time delay Delta such that omega Delta is less than 1.0, said second positive input adapted to be supplied with the analog input voltage signal in substantially undistorted form and merely being delayed by the time delay Delta from the undelayed signal applied to said second negative input upon passage through said second time delay network whereby said second comparator provides a continuous comparison of the amplitudes of the undelayed and delayed analog input voltage signal, the output of said second comparator being a binary logic voltage signal wherein the high state thereof corresponds to the time of negative polarity of the slope of the waveform of the analog input voltage signal, and a first binary logic gate having a first input connected to the output of said first comparator and a second input connected to the output of said second comparator, the output of said first logic gate being a short duration pulse occurring each time the slope of the waveform of the analog input voltage signal becomes zero.
Claim 8
Dependent Claim
30 words
The electrical circuit set forth in claim 6 and further comprising means for electrically isolating the inputs of said first voltage comparator from the inputs of said second voltage comparator.
Claim 9
Dependent Claim
107 words
The electrical circuit set forth in claim 7 wherein said electrical isolating means comprises a first electronic operational amplifier having a first input connected to a first juncture supplied with the analog input voltage signal, the output of said first operational amplifier connected to a second juncture which supplies the analog input voltage signal to said first positive and negative inputs of said first voltage comparator, a second electronic operational amplifier having a first input connected to said first juncture and the output connected to a third juncture which supplies the analog input voltage signal to said second positive and negative inputs of said second voltage comparator.
Claim 10
Dependent Claim
42 words
The electrical circuit set forth in claim 8 wherein said first and second operational amplifiers each have equal value resistances in the first inputs thereof and the same equal value resistances in negative feedback circuits thereof to thereby provide unity voltage gain.
Claim 11
Dependent Claim
56 words
The electrical circuit set forth in claim 9 and further comprising a second binary logic gate connected between the output of said first comparator and the first input of said first logic gate, and a third binary logic gate connected between the output of said second comparator and the second input of said first logic gate.
Claim 12
Dependent Claim
61 words
The electrical circuit set forth in claim 10 and further comprising a fourth binary logic gate connected to the output of said first logic gate, said second and third logic gates functioning to sharpen the edges of the pulse outputs of said comparators, and said fourth logic gate providing a sign reversal for the pulse output of said first logic gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-25 | 1975-10-25 | 1976-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-25 | 1979-10-25 | 1980-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-25 | 1983-10-25 | 1984-04-25 | $7700.00 | Window Closed / Lapsed |