Electrical circuitry for logarithmic conversion

Claim 2

In combination with a logarithmic conversion circuit, a memory circuit connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying the stored signal value to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuit from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 3

The combination as claimed in claim 1 wherein said logarithmic conversion circuit employs a semi-conductor junction as a logarithmic impedance device.

Claim 4

In combination with a logarithmic conversion circuit, a memory circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, said memory circuit having an input connected to the output of said logarithmic conversion circuit and an output, a background current range switch connected in circuit between the output of said memory circuit and said logarithmic conversion circuit, means for applying the signal value stored in said memory circuit to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuit from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 5

In combination with a logarithmic conversion circuit, a memory circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, said memory circuit having an input connected to the output of said logarithmic conversion circuit and an output, a background current range switch connected in circuit between the output of said memory circuit and said logarithmic conversion circuit, means for applying the signal value stored in said memory circuit to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuit from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 6

In combination, a logarithmic conversion circuit, means for adjusting the amplification factor of said logarithmic conversion circuit, a memory circuit connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying the stored signal value to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuiT from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 7

In combination, a logarithmic conversion circuit, means for adjusting the amplification factor of said logarithmic conversion circuit, a memory circuit connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying the stored signal value to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuiT from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 8

The combination as claimed in claim 4 wherein said amplification adjusting means includes a digitally controlled voltage divider network.

Claim 9

The combination as claimed in claim 5 wherein said digitally controlled voltage divider network includes a first section that defines a digital value and a second section that defines a multiplication factor.

Claim 10

In combination, a logarithmic conversion circuit including a converter transistor and a reference transistor connected in differential pair relation, a memory circuit connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying a current as a function of the stored signal value to said reference transistor of said differential pair as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuit from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 11

In combination, a logarithmic conversion circuit including a converter transistor and a reference transistor connected in differential pair relation, a memory circuit connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying a current as a function of the stored signal value to said reference transistor of said differential pair as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit while maintaining the application of said balancing reference signal to said logarithmic conversion circuit from said memory circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 12

The combination as claimed in claim 7 and further including a background current range switch connected in circuit between said memory circuit and the reference transistor of said differential pair.

Claim 13

The circuit as claimed in claim 7 and further including an operatinal amplifier coupled to each transistor of said differential pair, each transistor being connected in the feedback loop of its corresponding operational amplifier.

Claim 14

In combination with a logarithmic conversion circuit, a memory circuit including a storage capacitor connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying the stored signal value to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit including a switch having a high impedance in its open condition so that a charge on said capacitor as a function of the background signal is maintained and generates a balancing reference signal and applies said reference signal from said memory circuit to said logarithmic conversion circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 15

In combination with a logarithmic conversion circuit, a memory circuit including a storage capacitor connected to the output of said logarithmic conversion circuit for storing an output signal from said logarithmic conversion circuit as a function of a background signal applied to the input of said logarithmic conversion circuit, means for applying the stored signal value to said logarithmic conversion circuit as a balancing reference signal so that the output signal of said logarithmic conversion circuit is zero, and means for disconnecting said memory circuit from the output of said logarithmic conversion circuit including a switch having a high impedance in its open condition so that a charge on said capacitor as a function of the background signal is maintained and generates a balancing reference signal and applies said reference signal from said memory circuit to said logarithmic conversion circuit so that said logarithmic conversion circuit in response to a signal representative of a sample to be measured applied to the input of the logarithmic conversion circuit produces an output signal that is the difference between the logarithm of said background signal and the logarithm of said sample signal.

Claim 16

A logarithmic converter circuit comprising an input, an output, a converter transistor and a reference transistor connected in differential pair relation between said input and said output for providing a signal at said output as a logarithmic function of a signal applied at said input, an operational amplifier connected in circuit with each said transistor, circuitry including storage means for applying an output of said logarithmic converter circuit to said reference transistor and switch means conNected between said output of said logarithmic converter circuit and said storage means for interrupting the application of said signal to said storage means during a sample measurement operation while said storage means continues to apply a signal to said reference transistor so that said circuit produces a data signal that is incrementally related to a background signal.

Claim 17

A logarithmic converter circuit comprising an input, an output, a converter transistor and a reference transistor connected in differential pair relation between said input and said output for providing a signal at said output as a logarithmic function of a signal applied at said input, an operational amplifier connected in circuit with each said transistor, circuitry including storage means for applying an output of said logarithmic converter circuit to said reference transistor and switch means conNected between said output of said logarithmic converter circuit and said storage means for interrupting the application of said signal to said storage means during a sample measurement operation while said storage means continues to apply a signal to said reference transistor so that said circuit produces a data signal that is incrementally related to a background signal.

Claim 18

The circuit as claimed in claim 11 and further including a background current range switch connected in circuit between said memory circuit and the reference transistor of said differential pair.

Claim 19

A logarithmic converter circuit comprising an input, an output, a converter transistor and a reference transistor connected in differential pair relation between said input and said output for providing a signal at said output as a logarithmic function of a signal applied at said input, means for adjusting the amplification factor of said logarithmic converter circuit, circuitry including storage means for applying an output of said logarithmic converter circuit to said reference transistor, and switch means connected between said output of said logarithmic converter circuit and said storage means for interrupting the application of said signal to said storage means during a sample measurement operation while said storage means continues to apply a signal to said reference transistor so that said circuit produces a data signal that is incrementally related to a background signal

Claim 20

A logarithmic converter circuit comprising an input, an output, a converter transistor and a reference transistor connected in differential pair relation between said input and said output for providing a signal at said output as a logarithmic function of a signal applied at said input, means for adjusting the amplification factor of said logarithmic converter circuit, circuitry including storage means for applying an output of said logarithmic converter circuit to said reference transistor, and switch means connected between said output of said logarithmic converter circuit and said storage means for interrupting the application of said signal to said storage means during a sample measurement operation while said storage means continues to apply a signal to said reference transistor so that said circuit produces a data signal that is incrementally related to a background signal

Claim 21

The circuit as claimed in claim 13 wherein said amplification adjusting means includes a digitally controlled voltage divider network.

Claim 22

The circuit as claimed in claim 14 and further including a temperature compensation network connected to said amplification factor adjusting means for reducing the temperature coefficient of the volts/decade gain.

Claim 23

The circuit as claimed in claim 14 wherein said digitally controlled voltage divider network includes a first section that defines a digital value and a second section that defines a multiplication factor.

Claim 24

The circuit as claimed in claim 16 wherein said storage means is a capacitor connected in the feedback loop of an operational amplifier and said switch means has a high impedance in its open condition so that a charge on said capacitor as a function of the background signal is maintained and generates a balancing reference signal for application to said reference transistor.

Claim 25

The circuit as claimed in claim 15 and further including a background current range switch connected in circuit between said memory circuit and the reference transistor of said differential pair.

Claim 26

The circuit as claimed in claim 18 and further including a temperature compensation network connected to said voltage divider network for reducing the temperature coefficient of the volts/decade gain.