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US3657664A Expired / Lapsed US ⏱️ 0.0 years remaining

Frequency synthesizer

Assignee: COMMUNICATIONS ASSOCIATES Inc
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Filing: 1970-10-02
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Granted: 1972-04-18
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Expires: 1990-10-02
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Abstract

Abstract A frequency synthesizer having a phase lock loop for regulating a voltage controlled oscillator with reference to a stable oscillator frequency. The desired frequency is set on decade switches. An encoder converts the frequency value to a binary coded decimal equivalent nine''s complement number and presets a decade counter. An offset frequency is preintroduced into the counter by fixing the maximum count. Upon counting the maximum count, a shift register is triggered and during the shifting operation, the system is reset. The maximum count is reduced by the number of stages in the shift register. A steering voltage generator incorporating a staircase generator and an electronically switched filter is placed in parallel with the phase lock loop, and provides a coarse tuning of the voltage controlled oscillator.

Inventors

  • 👤 Werner Brack

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 03:29
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/187

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 286 words
A frequency synthesizer including: a. signal producing means for generating a reference signal having a precise predetermined frequency; b. a voltage controlled oscillator tunable in discrete frequency steps over a predetermined frequency range and producing an output signal; c. means for tuning said oscillator to a predetermined output frequency value; d. encoding means for converting said frequency value into its equivalent nine''s complement and formating said last number into binary coded decimal form; e. a shift register having a plurality of stages, f. a presettable counter, having a maximum count equal to the upper frequency limit of said synthesizer less the number of stages in the shift register, said binary coded decimal equivalent nine''s complement number being applied to said counter to fix the beginning counting number, and said counter counting said output pulses from said voltage controlled oscillator; g. coincidence means for providing a signal at the occurrence of the maximum count in said counters, said signal activating said shift registers to shift at the occurrence of each subsequent output pulse from said voltage controlled oscillator until all said stages have shifted; h. gate means for producing a feedback signal when all said stages have shifted; i. resetting means for presetting said presettable counter to its initial conditions during the operation of said shift register; j. a phase detector coupled to said signal producing means and said gate means, said phase detector responding to said reference signal and to said feedback signal for producing an error signal related to the difference between said reference signal and said feedback signal; and k. network means for applying said error signal to said voltage controlled oscillator to adjust the frequency of said oscillator to eliminate said phase displacement.
Claim 2
Dependent Claim 286 words
A frequency synthesizer including: a. signal producing means for generating a reference signal having a precise predetermined frequency; b. a voltage controlled oscillator tunable in discrete frequency steps over a predetermined frequency range and producing an output signal; c. means for tuning said oscillator to a predetermined output frequency value; d. encoding means for converting said frequency value into its equivalent nine''s complement and formating said last number into binary coded decimal form; e. a shift register having a plurality of stages, f. a presettable counter, having a maximum count equal to the upper frequency limit of said synthesizer less the number of stages in the shift register, said binary coded decimal equivalent nine''s complement number being applied to said counter to fix the beginning counting number, and said counter counting said output pulses from said voltage controlled oscillator; g. coincidence means for providing a signal at the occurrence of the maximum count in said counters, said signal activating said shift registers to shift at the occurrence of each subsequent output pulse from said voltage controlled oscillator until all said stages have shifted; h. gate means for producing a feedback signal when all said stages have shifted; i. resetting means for presetting said presettable counter to its initial conditions during the operation of said shift register; j. a phase detector coupled to said signal producing means and said gate means, said phase detector responding to said reference signal and to said feedback signal for producing an error signal related to the difference between said reference signal and said feedback signal; and k. network means for applying said error signal to said voltage controlled oscillator to adjust the frequency of said oscillator to eliminate said phase displacement.
Claim 3
Dependent Claim 48 words
The frequency synthesizer as in claim 1 wherein the input to said gate means is directly from said voltage controlled oscillator such that when all stages of said shift register have shifted, said gate means are enabled to permit said output pulses to pass as the feedback signal.
Claim 4
Dependent Claim 39 words
The frequency synthesizer as in claim 2 wherein said output pulses from said voltage controlled oscillator are AC signals and further including wave shaping means interposed between said voltage controlled oscillator and said counter, shift register and gate means.
Claim 5
Dependent Claim 45 words
The frequency synthesizer as in claim 1 further including voltage generating means, the input to which is said error signal, and producing a voltage level proportionate to said error signal, said voltage level being applied to said voltage controlled oscillator as a coarse tuning voltage.
Claim 6
Dependent Claim 59 words
The frequency synthesizer of claim 4, wherein said voltage generating means includes a staircase voltage generator, producing a sweep voltage, a summing amplifier for combining all said stepwise voltage levels, a lead compensation network, a lag compensation network, and an electronic switch responsive to an out-of-lock condition and being automatically disconnected during the tuning of said voltage controlled oscillator.
Claim 7
Dependent Claim 46 words
The frequency synthesizer of claim 1, wherein said voltage controlled oscillator comprises a plurality of oscillators each tunable over a narrow band of said frequency range and further including selection means responsive to said decade switches for selecting the appropriate one of said plurality of oscillators.
Claim 8
Dependent Claim 33 words
The frequency synthesizer of claim 1, wherein the maximum count includes the value of an offset frequency, and the number set on said decade switches is the desired frequency less said offset frequency.
Claim 9
Dependent Claim 41 words
A frequency syntheSizer as in claim 1, wherein said network means includes a first feedback loop having a wide bandwidth and low gain for coarse tuning, and a second feedback loop having a narrow bandwidth and high gain for fine tuning.
Claim 10
Dependent Claim 33 words
A frequency synthesizer as in claim 8, wherein said second feedback loop includes electronic switching means capable of controlling the time constant of said second feedback loop and responsive to an out-of-lock condition.
Claim 11
Dependent Claim 41 words
A frequency synthesizer as in claim 9, wherein said electronic switch comprises a field effect transistor which disconnects a large time constant circuit at the occurrence of an out-of-lock condition, and reinserts said large time constant circuit during lock up conditions.
Claim 12
Dependent Claim 22 words
The frequency synthesizer of claim 1 wherein said means for tuning said oscillator to a predetermined output frequency value comprise decade switches.

References Cited (Backward Citations)

US3484712A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-04-18 1975-10-18 1976-04-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-04-18 1979-10-18 1980-04-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-04-18 1983-10-18 1984-04-18 $7700.00 Window Closed / Lapsed

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