US3657571A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state timer
Assignee: Hamilton Watch Co
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Filing: 1970-05-21
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Granted: 1972-04-18
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Expires: 1990-05-21
Abstract
Abstract Disclosed is a timer of all solid state components and primarily formed from integrated circuits. The timer comprises a very low frequency oscillator coupled through a divider to an output circuit. In one embodiment, the timer is used to self-destruct a land mine after about twelve hours. In another, it produces an output from a magnetic core ring counter after about a year. Complementary MOSFET''s are used for the circuit components to minimize power consumption in both embodiments.
Inventors
- 👤 Vincent W Martin
- 👤 Bruce G Steiner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:58
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; H03K17/284; F; F42; F42C; F42C11/00; F42C11/06; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
89 words
A timer comprising an integrated circuit oscillator operating at a frequency below 1 Hz, and an integrated circuit divider coupled to the output of said oscillator, said oscillator and divider being formed of complementary MOSFET''s whereby said timer requires a minimum of energy, a logic circuit coupled to the output of said divider, said logic circuit comprising a multiple input NAND gate, each input of said gate being coupled to a different stage of said divider, and a magnetic core ring counter coupled to the output of said gate.
Claim 2
Dependent Claim
89 words
A timer comprising an integrated circuit oscillator operating at a frequency below 1 Hz, and an integrated circuit divider coupled to the output of said oscillator, said oscillator and divider being formed of complementary MOSFET''s whereby said timer requires a minimum of energy, a logic circuit coupled to the output of said divider, said logic circuit comprising a multiple input NAND gate, each input of said gate being coupled to a different stage of said divider, and a magnetic core ring counter coupled to the output of said gate.
Claim 3
Dependent Claim
18 words
A timer according to claim 1 including a pulse shaper coupling said NAND gate to said ring counter.
Claim 4
Dependent Claim
15 words
A timer according to claim 2 wherein said pulse shaper includes a silicon controlled rectifier.
Claim 5
Dependent Claim
45 words
A timer comprising an oscillator operating at a frequency below 1 Hz., a divider coupled to said oscillator to divide the oscillator output, a switch coupled to receive an output from said divider, and including a trembler switch coupled to the output of said divider.
Claim 6
Dependent Claim
45 words
A timer comprising an oscillator operating at a frequency below 1 Hz., a divider coupled to said oscillator to divide the oscillator output, a switch coupled to receive an output from said divider, and including a trembler switch coupled to the output of said divider.
Claim 7
Dependent Claim
84 words
A timer comprising an integrated circuit oscillator operating at a frequency below 1 Hz., an integrated circuit divider coupled to the output of said oscillator, said oscillator and divider being formed of complementary MOSFET''s whereby said timer requires a minimum of energy, a logic circuit coupled to the output of said divider, said logic circuit comprising a 2-input NAND gate, the output of said divider being coupled to one gate input, and a time delay circuit coupled to the other input of said gate.
Claim 8
Dependent Claim
84 words
A timer comprising an integrated circuit oscillator operating at a frequency below 1 Hz., an integrated circuit divider coupled to the output of said oscillator, said oscillator and divider being formed of complementary MOSFET''s whereby said timer requires a minimum of energy, a logic circuit coupled to the output of said divider, said logic circuit comprising a 2-input NAND gate, the output of said divider being coupled to one gate input, and a time delay circuit coupled to the other input of said gate.
Claim 9
Dependent Claim
16 words
A timer according to claim 5 including a trembler switch coupled to said one gate input.
Claim 10
Dependent Claim
20 words
A timer according to claim 6 wherein said time delay circuit comprises an arming delay circuit for a land mine.
Claim 11
Dependent Claim
26 words
A timer according to claim 7 wherein said arming delay circuit comprises a resistor and a capacitor coupled between said other gate input and said divider.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-18 | 1975-10-18 | 1976-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-18 | 1979-10-18 | 1980-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-18 | 1983-10-18 | 1984-04-18 | $7700.00 | Window Closed / Lapsed |