Interconnection bus system

Claim 2

In a digital input/output system for transmitting and receiving logical data pulse signals among a plurality of equipments, said system comprising: a bus; a plurality of pairs of line driver and receiver circuits, each of said pairs for interconnecting a different one of said equipments to different points along and to both ends of said bus, one end of said bus being connected in common with line driver and receiver circuit of a first one of said equipments and to a first load impedance in series with a single fixed voltage potential, said fixed voltage potential connected between said first load impedance and a common reference potential; a second load impedance means being connected in parallel with said first load impedance; and, a pseudo power supply including a third impedance means connected between the other end of said bus and said common reference potential, said third impedance means including energy storage means for deriving energy for said pseudo power supply only from said data pulse signals and said fixed voltage potential.

Claim 3

A transmission line circuit comprising: a transmission line; a plurality of circuits for transmitting electrical signals to and from a series of input/output loads tapped to said transmission line at different points along the length thereof; a first load impedance connected to said line in common with a first in said serieS of input/output loads of said circuit; a source of voltage, said voltage connected between said first load impedance and ground potential; a first impedance network branch connected in parallel with said first load impedance, said first branch including energy storage means; and, a second impedance network branch including energy storage means, complementary to said first, said second branch being connected to said line between ground potential and a last in said series of input/output loads connected at the other end of said line.

Claim 4

A transmission line circuit comprising: a transmission line; a plurality of circuits for transmitting electrical signals to and from a series of input/output loads tapped to said transmission line at different points along the length thereof; a first load impedance connected to said line in common with a first in said serieS of input/output loads of said circuit; a source of voltage, said voltage connected between said first load impedance and ground potential; a first impedance network branch connected in parallel with said first load impedance, said first branch including energy storage means; and, a second impedance network branch including energy storage means, complementary to said first, said second branch being connected to said line between ground potential and a last in said series of input/output loads connected at the other end of said line.

Claim 5

A transmission line circuit, the combination comprising: a transmission line having a uniform characteristic impedance; a plurality of input/output circuits tapped to each end of said line and at different points along the length thereof; a source of voltage, said source of voltage being referenced to ground; a first impedance network, connected between one end of said line and said source of voltage in common with a first one of said input/output circuits, said network including energy storage means; and, a second impedance network branch connected between the other end of said line and said ground reference potential in common with a last one of said input/output circuits, said branch including energy storage means for supplying energy to said line derived only from said input/output circuits and said source.

Claim 6

A transmission line circuit, the combination comprising: a transmission line having a uniform characteristic impedance; a plurality of input/output circuits tapped to each end of said line and at different points along the length thereof; a source of voltage, said source of voltage being referenced to ground; a first impedance network, connected between one end of said line and said source of voltage in common with a first one of said input/output circuits, said network including energy storage means; and, a second impedance network branch connected between the other end of said line and said ground reference potential in common with a last one of said input/output circuits, said branch including energy storage means for supplying energy to said line derived only from said input/output circuits and said source.

Claim 7

An input/output data transfer bus system including a bus having a predetermined characteristic impedance, an input/output controller directly coupled to one end of said bus and a plurality of input/output devices interconnected for signal transmission to said system by a transistor line driver and receiver circuits having their output and input circuits respectively tapped to said bus at different points along the length thereof, each of said driver circuits including an output transistor of like conductivity type connected in a common emitter configuration and having an emitter electrode and a collector electrode, said emitter electrode being connected to ground potential and said collector electrode being directly coupled to said bus, said bus system further including; a first resistive element connected in series with the collector-emitter electrodes of said output transistor of said input/output controller, said first resistive element having a value to terminate said bus resistively in said characteristic impedance; a source of supply voltage potential, said source of supply voltage potential being directly connected between said first resistive element and ground; a first series combination of a second resistive element and a first energy storage element being connected in parallel with said first resistive element; and, a second series combination of a third resistive element and a second energy storage element complementary to the first, being directly connected between ground and the collector electrode of said output transistor of the input/output device directly coupled to the other end of said bus, whereby the impedance of said parallel combination of said first resistive element and said first series combination and the impedance of said second series combination are selected respectively to under and over terminate said bus in a value less and greater than said characteristic impedance thereby producing predictable multiple reflections for operating said bus as one which is directly coupled at both ends to a source of supply voltage.

Claim 8

An input/output data transfer bus system including a bus having a predetermined characteristic impedance, an input/output controller directly coupled to one end of said bus and a plurality of input/output devices interconnected for signal transmission to said system by a transistor line driver and receiver circuits having their output and input circuits respectively tapped to said bus at different points along the length thereof, each of said driver circuits including an output transistor of like conductivity type connected in a common emitter configuration and having an emitter electrode and a collector electrode, said emitter electrode being connected to ground potential and said collector electrode being directly coupled to said bus, said bus system further including; a first resistive element connected in series with the collector-emitter electrodes of said output transistor of said input/output controller, said first resistive element having a value to terminate said bus resistively in said characteristic impedance; a source of supply voltage potential, said source of supply voltage potential being directly connected between said first resistive element and ground; a first series combination of a second resistive element and a first energy storage element being connected in parallel with said first resistive element; and, a second series combination of a third resistive element and a second energy storage element complementary to the first, being directly connected between ground and the collector electrode of said output transistor of the input/output device directly coupled to the other end of said bus, whereby the impedance of said parallel combination of said first resistive element and said first series combination and the impedance of said second series combination are selected respectively to under and over terminate said bus in a value less and greater than said characteristic impedance thereby producing predictable multiple reflections for operating said bus as one which is directly coupled at both ends to a source of supply voltage.

Claim 9

The bus system of claim 4 wherein said second and said third resistive elements each have values selected to approximate said bus characteristic impedance.

Claim 10

The bus system of claim 4 wherein said first and second storage elements respectively are an inductor and a capacitor.

Claim 11

The bus system of claim 6 wherein the square root of the ratio of the value of inductance of said inductor to capacitance of said capacitor substantially equals the characteristic impedance of said bus.

Claim 12

The bus system of claim 7 whErein said bus has a predetermined time delay in one direction and said inductance and said capacitance are selected to give time constants of reflection greater than said delay.

Claim 13

The bus system of claim 4 wherein said first resistive element and said first series combination has an impedance whose value is less than said characteristic impedance for reflecting voltage signals negatively and said second series combination has an impedance whose value is greater than said characteristic impedance for reflecting voltage signals positively.

Claim 14

An input/output data transfer bus system including an input/output controller, IOC, and a series of input/output devices IOD-1 through IOD-n connected to said bus system by corresponding ones of a plurality of transistor line driver and receiver circuits, DC-m, RC-m, and DC-1, RC- 1 through DC-n, RC-n having their output and input circuits respectively tapped to said bus at different points, T-m and T-1 through T-n along the length thereof, each of said driver circuits, DC-m and DC-1 through DC-n including an output transistor, TR of like conductivity type and having an emitter electrode and a collector electrode, said emitter electrode being connected to ground potential and said collector electrode being directly coupled to said bus, said bus system further including; a collector load resistor, ZL, for said output transistor, TR-m, of said input/output controller, IOC, said resistor, ZL, having a value to terminate said bus in its characteristic resistance, Ro; a source of voltage potential, +V, said voltage potential being directly connected in series with resistor, ZL; a first series combination of a second resistor, R301, and a first energy storage element, X301, being connected in parallel with said first resistor; and, a second series combination of a third resistor, R201, and a second energy storage element, X201, being directly connected between ground and the collector electrode of said output transistor, TR-n, of the last input/output device, IOD-n, in said series.

Claim 15

An input/output data transfer bus system including an input/output controller, IOC, and a series of input/output devices IOD-1 through IOD-n connected to said bus system by corresponding ones of a plurality of transistor line driver and receiver circuits, DC-m, RC-m, and DC-1, RC- 1 through DC-n, RC-n having their output and input circuits respectively tapped to said bus at different points, T-m and T-1 through T-n along the length thereof, each of said driver circuits, DC-m and DC-1 through DC-n including an output transistor, TR of like conductivity type and having an emitter electrode and a collector electrode, said emitter electrode being connected to ground potential and said collector electrode being directly coupled to said bus, said bus system further including; a collector load resistor, ZL, for said output transistor, TR-m, of said input/output controller, IOC, said resistor, ZL, having a value to terminate said bus in its characteristic resistance, Ro; a source of voltage potential, +V, said voltage potential being directly connected in series with resistor, ZL; a first series combination of a second resistor, R301, and a first energy storage element, X301, being connected in parallel with said first resistor; and, a second series combination of a third resistor, R201, and a second energy storage element, X201, being directly connected between ground and the collector electrode of said output transistor, TR-n, of the last input/output device, IOD-n, in said series.

Claim 16

An input/output data transfer bus system including an input/output controller and a series of input/output devices interconnected to said system by a transistor line driver and receiver circuits having their output and input circuits respectively tapped to said bus at different points along the length thereof, each of said driver circuits including an output transistor of like conductivity type connected in the common emitter configuration and having an emitter electrode and a collector electrode, said emitter electrode being connected to ground potential and said collector electrode being directly coupled to said bus, said bus system further including; a collector load resistive element for said output transistor of said input/output controller, said resistive element having a value to terminate said bus in its characteristic resistance; a source of voltage, said voltage being directly connected in series with said load resistive element, said load resistive element in series with said voltage connected to provide a first unit of current; a first series combination of a second resistor and a first energy storage element being connected in parallel with said load resistive element, the impedance of said first combination in series with said voltage selected to provide a first unit of current changing at a first predetermined exponential rate; and, a second series combination of a third resistor and a second energy storage element, complementary to said first, being directly coupled between ground and the collector electrode of said output transistor of the last input/output device in said series, said second series combination selected to have an impedance value which provides a second unit of current, complementary to said first, changing at a sEcond exponential rate.

Claim 17

An input/output data transfer bus system including an input/output controller and a series of input/output devices interconnected to said system by a transistor line driver and receiver circuits having their output and input circuits respectively tapped to said bus at different points along the length thereof, each of said driver circuits including an output transistor of like conductivity type connected in the common emitter configuration and having an emitter electrode and a collector electrode, said emitter electrode being connected to ground potential and said collector electrode being directly coupled to said bus, said bus system further including; a collector load resistive element for said output transistor of said input/output controller, said resistive element having a value to terminate said bus in its characteristic resistance; a source of voltage, said voltage being directly connected in series with said load resistive element, said load resistive element in series with said voltage connected to provide a first unit of current; a first series combination of a second resistor and a first energy storage element being connected in parallel with said load resistive element, the impedance of said first combination in series with said voltage selected to provide a first unit of current changing at a first predetermined exponential rate; and, a second series combination of a third resistor and a second energy storage element, complementary to said first, being directly coupled between ground and the collector electrode of said output transistor of the last input/output device in said series, said second series combination selected to have an impedance value which provides a second unit of current, complementary to said first, changing at a sEcond exponential rate.

Claim 18

The system according to claim 10 wherein each of said resistors R201 and R301 have a value Ro, said first storage element X301 is an inductor, L1, having a predetermined value of inductance, said second storage element X201 is a capacitor, C1, having a predetermined value of capacitance and the coefficient of reflection K for each of said points T-m and T-n are defined as follows: K(T-m) 1/(2SL1/Ro+3) and K(T-n) 1/(2RoC1S+1).

Claim 19

The system according to claim 12 wherein the values for time constants defined by L1/Ro and RoC1 are selected to be equal.

Claim 20

The system according to claim 12 wherein the values for time constants defined by L1/Ro and RoC1 are selected to be unequal.

Claim 21

The system according to claim 11 wherein said first energy storage element and second energy storage elements are respectively an inductor and a capacitor.