US3656151A
Expired / Lapsed
US
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Digital function generation network
Assignee: Magnavox Electronic Systems Co
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Filing: 1970-03-26
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Granted: 1972-04-11
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Expires: 1990-03-26
Abstract
Abstract A scheme for transforming input digital information into output analog information where the output is a specified and not necessarily linear function of the input is disclosed. In its simplest form, the circuitry for achieving this result consists of a ladder network, a waveshaping impedance, and a signal generator connected in series. Each rung of the ladder network is a series impedance and gate circuit associated with a specified digital position in the input code and the corresponding impedance is weighted as a function of its positional significance. An output operational amplifier may optionally be provided which serves to invert and appropriately shift the output signal to achieve the desired output waveform.
Inventors
- 👤 William E Richeson Jr
- 👤 Mike B Feher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:01
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/26; G06G7/28; H; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
140 words
A digital to analog converter comprising: a plurality of conduct-no conduct gates, each adapted to be responsive to the status of one of the digit positions in an input digital code; a corresponding plurality of impedances, said impedances weighted in accordance with the particular digital code employed, each said impedance forming a series circuit with its corresponding gate and the thus formed plurality of gateimpedance circuits forming a plurality of parallel paths; a voltage source; a selectively variable waveshaping impedance, said voltage source said waveshaping impedance and said plurality of parallel paths forming a series circuit; and output means comprising an operational amplifier and responsive to the analog signal across said plurality of parallel paths to selectively shift and to selectively invert said analog signal so as to provide an analog output representation of a function of the digital input.
Claim 2
Dependent Claim
140 words
A digital to analog converter comprising: a plurality of conduct-no conduct gates, each adapted to be responsive to the status of one of the digit positions in an input digital code; a corresponding plurality of impedances, said impedances weighted in accordance with the particular digital code employed, each said impedance forming a series circuit with its corresponding gate and the thus formed plurality of gateimpedance circuits forming a plurality of parallel paths; a voltage source; a selectively variable waveshaping impedance, said voltage source said waveshaping impedance and said plurality of parallel paths forming a series circuit; and output means comprising an operational amplifier and responsive to the analog signal across said plurality of parallel paths to selectively shift and to selectively invert said analog signal so as to provide an analog output representation of a function of the digital input.
Claim 3
Dependent Claim
51 words
The converter of claim 1 wherein the digital code is a straight binary code of n bits and wherein if the impedance associated with the highest order bit gate is Z, then the impedance associated with the gate representing 2m is Z(2n 1 m) where 0 < or = m< n.
Claim 4
Dependent Claim
102 words
A circuit for generating an approximation to an arbitrary analog output waveform in response to a set of digital input signals comprising: digital input means; circuit means for generating a portion of an approximately hyperbolic output waveform in response to a sequential digital input of the form n1 0 and ni 1 ni+1; means for selectively shifting said waveform; and means responsive to said circuit means for selectively inverting said waveform wherein said circuit means comprises a ladder network, a signal generator, and a waveshaping impedance connected together in series, the output of said circuit means being taken across said ladder network.
Claim 5
Dependent Claim
102 words
A circuit for generating an approximation to an arbitrary analog output waveform in response to a set of digital input signals comprising: digital input means; circuit means for generating a portion of an approximately hyperbolic output waveform in response to a sequential digital input of the form n1 0 and ni 1 ni+1; means for selectively shifting said waveform; and means responsive to said circuit means for selectively inverting said waveform wherein said circuit means comprises a ladder network, a signal generator, and a waveshaping impedance connected together in series, the output of said circuit means being taken across said ladder network.
Claim 6
Dependent Claim
34 words
The circuit of claim 3 wherein said ladder network comprises a series of rungs, each rung comprising a series impedance and gate, said gate responsive to a specified digit of said digital input signal.
Claim 7
Dependent Claim
40 words
The circuit of claim 4 wherein if the impedance in the rung associated with the highest order bit is Z then the impedance associated with the rung representing 2m is Z(2n 1 m) where 0 < or = m< n.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-11 | 1975-10-11 | 1976-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-11 | 1979-10-11 | 1980-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-11 | 1983-10-11 | 1984-04-11 | $7700.00 | Window Closed / Lapsed |