Code conversion system

Claim 2

A code conversion system for summing conversion of m N trains of binary coded signals having a low repetition rate, where both m and N are integers not less than 2, said trains being divided into m groups each including N trains, said system comprising a circuit for performing a summing operation on the trains of low rate coded signals of the first group to produce N trains of summing conversion outputs of a first group, a circuit to produce a group of N carry signals from the first group of low rate trains of coded signals to the second group of low rate trains of coded signals, (m - 2) circuits each operable to perform a carry operation and a summing operation on a group of carry signals from an (n - 1)-th group of low rate trains of coded signals and an n-th group of low rate trains of coded signals to produce an n-th group of N trains of summing conversion outputs, n being a number from two to (m - 1), (m - 2) circuits each operable to produce a group of N carry signals from the n-th group of low rate trains to (n + 1)-th group of low rate trains, a circuit for performing a carry operation and a summing operation on the group of carry signals from the (m - 1)-th group of low rate trains and the m-th group of low rate trains of coded signals to produce an m-th group of N trains of summing conversion outputs, and m multiplexing circuits associated with each of the first to m-th groups of N trains of summing conversion outputs for multiplexing the summing conversion outputs of the respective groups into a single train of coded signals of a higher repetition rate on bit basis.

Claim 3

A code conversion system according to claim 1 in which the circuit to produce the first group of N trains of summing conversion outputs comprises a delay circuit for delaying a code conversion output corresponding to the last train of low rate coded signal by an amount corresponding to one bit period of the low rate train, a circuit to form an exclusive logical sum of the output of the delay circuit and a coded signal of the first low rate train to produce a low rate code conversion output for the first low rate train, and (N - 1) circuits each operable to form an exclusive logical sum of a low rate code conversion output corresponding to a (k - 1)-th train of low rate coded signals and a coded signal of the k-th low rate train, where k is an integer from two to N, thereby producing a low rate code conversion output for the k-th low rate train.

Claim 4

A code conversion system according to claim 1 in which the circuit to produce a group of N carry signals from the first group of low rate trains to the second group of low rate trains produces a carry signal for a k-th low rate train, k being a number from 1 to N, by forming a logical product of a coded signal of the k-th low rate train and the complement of a code conversion output corresponding to the coded signal of the k-th low rate train.

Claim 5

A code conversion system according to claim 1 in which the circuit operable to perform a carry operation and a summing operation on an n-th group of low rate trains of coded signals to produce an n-th group of N trains of low rate summing conversion outputs for any number of n from two to (m - 1) comprises a circuit to form an exclusive logical sum of k-th carry signal from an (n - 1-th group of low rate trains and a coded signal of a k-th low rate train of the n-th group to thereby perform a carry operation on the coded signal of the k-th low rate train of the n-th group for any number of k from one to N, a delay circuit for delaying the N-th train of coded signals after they have been subjected to said carry operation by an amount corresponding to one bit period of the low rate train, a circuit to form an exclusive logical sum of the output of the delay circuit and a coded signal of the first low rate train after it has been subjected to said carry operation to produce a low rate code conversion output for the first train, and (N - 1) circuits each operable to form an exclusive logical sum of a coded signal of a j-th low rate train and a coded signal of a (j - 1)-th low rate train after both of these coded signal have been subjected to said carry operation to produce a low rate code conversion output for the j-th train of the n-th group for any number of j from 2 to N.

Claim 6

A code conversion system according to claim 1 in which the circuit operable to perform a carry operation and a summing conversion on an n-th group of low rate trains of coded signals to produce an n-th group of N trains of low rate summing conversion outputs for any number of n from two to (m -1) comprises a delay circuit for delaying the N-th train of low rate coded signals after they have been subjected to the summing operation by an amount corresponding to one bit period of the low rate train, a circuit to form an exclusive logical sum of the output of the delay circuit and a coded signal of the first low rate train to produce a summing operation output for the first low rate train, (N - 1) circuits each operable to form an exclusive logical sum of a coded signal of a k-th low rate train and a coded signal of a (k - 1)-th low rate train to produce a summing operation output for the k-th low rate train for a number of k from two to N, and N circuits each operable to form an exclusive logical sum of a summing operation output for the j-th low rate train of the n-th group and a j-th carry signal from the (n - 1)-th group of low rate trains to produce a low rate summing conversion output for the j-th train of the n-th group for any number of j from 1 to N.

Claim 7

A code conversion system according to claim 1 in which the circuit operable to produce a group of N carry signals from an n-th group of low rate trains to an (n + 1-th group of low rate trains for any number of n from 2 to (m - 1) comprises N circuits each operable to produce a first carry signal by forming a logical produce of a low rate coded signal which is to be used as an input to a circuit to form an exclusive logical sum for the summing operation of a k-th train of low rate coded signals of the n-th group and the complement of the output from the exclusive logical sum circuit, where k is a number from one to N, further N circuits each operable to produce a second carry signal by forming a logical product of the two input trains of coded signals to a circuit which forms an exclusive logical sum for the carry operation of the k-th low rate train of coded signals, and additional N circuits each operable to form a logical sum of the first and second carry signals from the k-th low rate train to produce a carry signal to the k-th low rate train of the (n + 1-th group.

Claim 8

A code conversion system for differential conversion of m trains of binary coded signals of a high repetition rate, where m is a positive integer not less than 2, said system comprising m demultiplexing circuits operable to demultiplex on bit basis each of the first to m-th high rate trains of coded signals into a first to m-th groups each including N demultiplexed trains of lower rate coded signals, where N is a positive integer not less than two, a circuit for performing a differential operation on the demultiplexed lower rate trains of coded signals of the first group to produce a first group of N trains of converted, lower rate coded signals, a circuit to produce a group of N carry signals from the first group of lower rate trains to the second group of lower rate trains, (m - 2) circuits each operable to perform a differential operation and a carry operation on coded signals of demultiplexed lower rate trains of an n-th group and N carry signals from an (n - 1)-th group of lower rate trains to produce an n-th group of N trains of converted, lower rate coded signals for any number of n from two to (m - 1), further (m - 2) circuits each operable to produce a group of N carry signals from the n-th group of lower rate trains to the (n + 1)-th group of lower rate trains, and a circuit to perform a differential operation and a carry operation on coded signals of demultiplexed lower rate trains of the m-th group and N carry signals from the (m - 1)-th group of lower rate trains to produce an m-th group of N trains of converted, lower rate coded signals.

Claim 9

A code conversion system for differential conversion of m trains of binary coded signals of a high repetition rate, where m is a positive integer not less than 2, said system comprising m demultiplexing circuits operable to demultiplex on bit basis each of the first to m-th high rate trains of coded signals into a first to m-th groups each including N demultiplexed trains of lower rate coded signals, where N is a positive integer not less than two, a circuit for performing a differential operation on the demultiplexed lower rate trains of coded signals of the first group to produce a first group of N trains of converted, lower rate coded signals, a circuit to produce a group of N carry signals from the first group of lower rate trains to the second group of lower rate trains, (m - 2) circuits each operable to perform a differential operation and a carry operation on coded signals of demultiplexed lower rate trains of an n-th group and N carry signals from an (n - 1)-th group of lower rate trains to produce an n-th group of N trains of converted, lower rate coded signals for any number of n from two to (m - 1), further (m - 2) circuits each operable to produce a group of N carry signals from the n-th group of lower rate trains to the (n + 1)-th group of lower rate trains, and a circuit to perform a differential operation and a carry operation on coded signals of demultiplexed lower rate trains of the m-th group and N carry signals from the (m - 1)-th group of lower rate trains to produce an m-th group of N trains of converted, lower rate coded signals.

Claim 10

A code conversion system according to claim 7 in which the circuit for performing a differential operation on the coded signals of demultiplexed lower rate trains of the first group to produce a first group of N trains of converted, lower rate coded signals comprises a delay circuit for delaying the coded signals of the demultiplexed N-th lower rate train by an amount corresponding to one bit period of the lower rate train, a circuit to form an exclusive logical sum of the output of the delay circuit and a coded signal of the first demultiplexed lower rate train to produce a converted coded signal for the first lower rate train, and (N - 1) circuits each operable to form an exclusive logical sum of a coded signal of a k-th demultiplexed lower rate train and a coded signal of a (k - 1)-th demultiplexed lower rate train to produce a converted coded signal for the k-th lower rate train for a number of k from 2 to N.

Claim 11

A code conversion system according to claim 7 in which the circuit to produce a group of N carry signals from the first group of demultiplexed lower rate trains to the second group of demultiplexed lower rate trains comprises N circuits each operable to produce a carry signal to a k-th demultiplexed lower rate train of the second group by forming a logical product of the complement of a coded signal of the k-th demultiplexed lower rate train of the first group and a converted, lower rate coded signal for said k-th train of the first group for a number of k from 1 to N.

Claim 12

A code conversion system according to claim 7 in which the circuit operable to perform a differential operation and a carry operation on coded signals of demultiplexed lower rate trains of an n-th group and N carry signals from an (n - 1)-th group of demultiplexed lower rate trains to produce an n-th group of N trains of converted, lower rate coded signals for a number of n from two to (m - 1) comprises a delay circuit for delaying the coded signals of the N-th demultiplexed lower rate train of the n-th group by an amount corresponding to one bit period of the lower rate train, a circuit to perform a differential operation for the first demultiplexed lower rate train of coded signals by forming an exclusive logical sum of the output of the delay circuit and a coded signal of the first demultiplexed lower rate train, (N - 1) circuits each operable to perform a differential operation for a k-th demultiplexed lower rate train of coded signals by forming an exclusive logical sum of a coded signal of a (k - 1)-th demultiplexed lower rate train and a coded signal of the k-th demultiplexed lower rate train for a number of k from two to N, and N circuits each operable to form an exclusive logical sum of a coded signal of a j-th demultiplexed lower rate train which has been subjected to said differential operation and a j-th carry signal from the (n - 1)-th group of demultiplexed lower rate trains to produce a converted, lower rate coded signal for the j-th train of the n-th group for a number of j from 1 to N.

Claim 13

A code conversion system according to claim 7 in which the circuit operable to perform a differential operation and a carry operation on coded signals of demultiplexed lower rate trains of an n-th group and N carry signals from an (n - 1)-th group of demultiplexed lower rate trains to produce an n-th group of N trains of converted, lower rate coded signals for a number of from two to (m - 1) comprises N circuits each operable to perform a carry operation on a j-th demultiplexed lower rate train of the n-th group by forming an exclusive logical sum of a coded signal of the j-th demultiplexed lower rate train of the n-th group and a j-th carry signal from the (n - 1)-th group of demultiplexed lower rate trains for a number of j from one to N, a delay circuit for delaying the coded signals of the N-th lower rate train of the n-th group after they have been subjected to said carry operation by an amount corresponding to one bit period of the lower rate train, a circuit to form an exclusive logical sum of the output of the delay circuit and a coded signal of the first lower rate train of the n-th group after it has been subjected to said carry operation to produce a converted, lower rate coded signal for the first demultiplexed lower rate train of the n-th group, and (N - 1) circuits each operable to form an exclusive logical sum of a coded signal of a k-th lower rate train after it has been subjected to said carry operation and a coded signal of a (k - 1-th lower rate train after it has been subjected to said carry operation to produce a converted, lower rate coded signal for the k-th lower rate train of the n-th group for a number of k from 2 to N.

Claim 14

A code conversion system according to claim 7 in which the circuit operable to produce a group of N carry signals from an n-th group of lower rate trains to an (n + 1)-th group of lower rate trains for a number of n from two to (m - 1) comprises N circuits each operable to produce a first carry signal by forming a logical product of the complement of a lower rate coded signal which is to be used as an input to a circuit to form an exclusive logical sum for the differential operation of a k-th demultiplexed lower rate train of the (n + 1)-th group and the output of the exclusive logical sum circuit, where k is a number from one to N, further N circuits each operable to produce a second carry signal by forming a logical product of the output from a circuit which forms an exclusive logical sum for the carry operation of the k-th demultiplexed lower rate train of coded signals and a carry signal from the (n - 1-th group of demultiplexed lower rate trains to the k-th demultiplexed lower rate train of the n-th group, and additional N circuits each operable to form an exclusive logical sum of the first and second carry signals from the k-th lower rate train to produce a carry signal to a k-th demultiplexed lower rate train of the (n + 1-th group.

Claim 15

A binary code conversion system, comprising: a source of N trains of binary coded signals having a low repetition rate, N being an integer of at least 2; N Exclusive OR logical sum circuits, each having one input activated by a different one of said signal trains; N-1 leads, each connecting an output of one of said sum circuits to a second input of a next succeeding sum circuit, whereby each of N-1 sum circuits produces a logical sum of a code conversion output of a preceding sum circuit and a corresponding kth train of (K-1) trains of low repetition rate code signals; k being at least a two integer of integers 2 through N; a delay circuit providing a one bit delay corresponding to one bit of said low repetition rate signals for connecting an output of a last of said N-1 sum circuits and a second input of a first of said N sum circuits to activate said first sum circuit to produce a logical sum of the code conversion output of said last sum circuit and said code signal train activating said first sum circuit input; and a multiplexer for multiplexing said logical sums in said respective sum circuit outputs on a bit basis into a higher repetition rate train beginning with said first sum circuit and progressing in turn to said last sum circuit and then recurrinG back to said first sum circuit.

Claim 16

A binary code conversion system, comprising: a source of N trains of binary coded signals having a low repetition rate, N being an integer of at least 2; N Exclusive OR logical sum circuits, each having one input activated by a different one of said signal trains; N-1 leads, each connecting an output of one of said sum circuits to a second input of a next succeeding sum circuit, whereby each of N-1 sum circuits produces a logical sum of a code conversion output of a preceding sum circuit and a corresponding kth train of (K-1) trains of low repetition rate code signals; k being at least a two integer of integers 2 through N; a delay circuit providing a one bit delay corresponding to one bit of said low repetition rate signals for connecting an output of a last of said N-1 sum circuits and a second input of a first of said N sum circuits to activate said first sum circuit to produce a logical sum of the code conversion output of said last sum circuit and said code signal train activating said first sum circuit input; and a multiplexer for multiplexing said logical sums in said respective sum circuit outputs on a bit basis into a higher repetition rate train beginning with said first sum circuit and progressing in turn to said last sum circuit and then recurrinG back to said first sum circuit.

Claim 17

A code conversion system for deriving N trains of binary code signals of low repetition rate from a high repetition rate code conversion train of Exclusive OR logical sum signals formed on a bit basis by N-1 Exclusive OR logical sum circuits whose inputs are actuated by (k-1) trains of said code signals of low repetition rate and code conversion signal outputs of preceding Exclusive OR logical sum circuit and another Exclusive OR logical sum circuit whose inputs are activated by another train of said code signals of low repetition rate and a code conversion signal output provided with a one bit delay corresponding to a one bit of said low repetition rate signals as derived from a last of said N-1 Exclusive OR logical sum circuits; N being an integer of at least 2 and k being an integer selected from integers 2 through N, comprising: a demultiplexer for demultiplexing said code conversion signal train of high repetition rate on a bit basis into N trains of code conversion signals of low repetition rate; N Exclusive OR logical subtraction circuits, each having one input activated by a different one of said last-mentioned N trains of low repetition rate code conversion signals; N-1 leads, each connecting an output of one said sum circuits to a second input of a next succeeding subtraction circuit, whereby each of N-1 subtraction circuits responsive to a low repetition rate code conversion signal of a preceding subtraction circuit and a corresponding k-th low repetition rate code conversion signal train of (k-1) low repetition rate code conversion signal trains produces one of said N binary code signal trains of low repetition rate; and a delay circuit providing a one bit delay corresponding to one bit of said low repetition rate code signals for connecting an input of a last of said N-1 subtraction circuits to a second input of a first of said N subtraction circuits for producing another of said N binary code signal trains of low repetition rate.

Claim 18

A code conversion system for deriving N trains of binary code signals of low repetition rate from a high repetition rate code conversion train of Exclusive OR logical sum signals formed on a bit basis by N-1 Exclusive OR logical sum circuits whose inputs are actuated by (k-1) trains of said code signals of low repetition rate and code conversion signal outputs of preceding Exclusive OR logical sum circuit and another Exclusive OR logical sum circuit whose inputs are activated by another train of said code signals of low repetition rate and a code conversion signal output provided with a one bit delay corresponding to a one bit of said low repetition rate signals as derived from a last of said N-1 Exclusive OR logical sum circuits; N being an integer of at least 2 and k being an integer selected from integers 2 through N, comprising: a demultiplexer for demultiplexing said code conversion signal train of high repetition rate on a bit basis into N trains of code conversion signals of low repetition rate; N Exclusive OR logical subtraction circuits, each having one input activated by a different one of said last-mentioned N trains of low repetition rate code conversion signals; N-1 leads, each connecting an output of one said sum circuits to a second input of a next succeeding subtraction circuit, whereby each of N-1 subtraction circuits responsive to a low repetition rate code conversion signal of a preceding subtraction circuit and a corresponding k-th low repetition rate code conversion signal train of (k-1) low repetition rate code conversion signal trains produces one of said N binary code signal trains of low repetition rate; and a delay circuit providing a one bit delay corresponding to one bit of said low repetition rate code signals for connecting an input of a last of said N-1 subtraction circuits to a second input of a first of said N subtraction circuits for producing another of said N binary code signal trains of low repetition rate.