US3654448A
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US
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Instruction execution and re-execution with in-line branch sequences
Assignee: International Business Machines Corp
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Filing: 1970-06-19
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Granted: 1972-04-04
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Expires: 1990-06-19
Abstract
Abstract Instruction re-execution for error recovery is enhanced by function skipping conditional branches in the execution control sequence. Branches continuing the main execution stream control execution and re-execution of basic functions and ancillary verification and saving functions required for error recovery. The latter functions are organized for rapid execution so as not to unduly lessen the execution throughput rate of the system. Ancillary functions include checking of particular basic function result signals and associated ancillary function control signals, ''scratchpad'' saving of the particular function result signals in fast access general purpose buffer storage and setting of reexecution branch conditions to signal for skipping of basic functions when re-executing instructions after basic function result signals have been saved. Function skipping branches are taken therefor only in late re-execution; i.e. only when the reexecution branch condition for function skipping has been set prior to occurrence of error in execution. In the function skipping branch previously saved basic function result signals required for continued execution are obtained directly from fast access buffer storage, thereby eliminating original operand signal handling and arithmetic or logic processes of the skipped function. This is especially useful as the associated operand signals may no longer be available at re-execution time. The reexecution branch condition for function skipping is reset at conclusion of each instruction execution control sequence. Foregoing control organization has the advantage that verified and properly saved basic function results need not be reprocessed and recalculated during error recovery. Also by virtue of the standardized organization of the branch the controls may be adapted piecemeal to a variety of different system recovery functions with minimal cost/performance degradation.
Inventors
- 👤 Donald C Hitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/38; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
267 words
In a data processing system having program storage, fastaccess storage, error checking facility and a sequence control section adapted to produce successive first and second control sequences of multiple elementary processing operations for executing a program instruction, said first sequence comprising calculation and verification in said checking facility of a relative address quantity by arithmetic summation of displacement and base register quantities designated by the instruction intelligence and said second sequence comprising utilization of said relative address quantity to address said program storage in a further processing operation relative to said relative address involving participation of said checking facility, the control section improvement comprising: adaptation of said control section to provide operations ancillary to error recycling within said first sequence; said ancillary operations including operations relative to said fast-access buffer storage to save therein a manifestation of the relative address produced and checked earlier in said first sequence and a terminal operation to set a skip branch condition; said control section adapted further to provide operation to reset said skip branch condition prior to initial entry into said instruction execution control sequence; and upon completion of said second sequence; said control section adapted further to respond to error indication by said checking facility to provide re-entry into said instruction execution control sequence at a stage subsequent to the said skip branch reset operation, with selective skipping of said first sequence conditioned thereby upon earlier occurrence of said skip branch set operation, said first sequence skipping including control operation to Provide for retrieval of said saved relative address from said fastaccess store followed directly by said second sequence.
Claim 2
Dependent Claim
267 words
In a data processing system having program storage, fastaccess storage, error checking facility and a sequence control section adapted to produce successive first and second control sequences of multiple elementary processing operations for executing a program instruction, said first sequence comprising calculation and verification in said checking facility of a relative address quantity by arithmetic summation of displacement and base register quantities designated by the instruction intelligence and said second sequence comprising utilization of said relative address quantity to address said program storage in a further processing operation relative to said relative address involving participation of said checking facility, the control section improvement comprising: adaptation of said control section to provide operations ancillary to error recycling within said first sequence; said ancillary operations including operations relative to said fast-access buffer storage to save therein a manifestation of the relative address produced and checked earlier in said first sequence and a terminal operation to set a skip branch condition; said control section adapted further to provide operation to reset said skip branch condition prior to initial entry into said instruction execution control sequence; and upon completion of said second sequence; said control section adapted further to respond to error indication by said checking facility to provide re-entry into said instruction execution control sequence at a stage subsequent to the said skip branch reset operation, with selective skipping of said first sequence conditioned thereby upon earlier occurrence of said skip branch set operation, said first sequence skipping including control operation to Provide for retrieval of said saved relative address from said fastaccess store followed directly by said second sequence.
Claim 3
Dependent Claim
79 words
The control section of claim 1 wherein said checking facility includes: first means for checking said relative address quantity in the course of development of said quantity; second means for checking the control signals which control said ancillary saving and skip branch condition setting operations; and means controlled by said first and second checking means for delaying execution of said ancillary operations and conditioning said delayed execution upon completion of the checking of said address quantity and control signals.
Claim 4
Dependent Claim
124 words
In a data processing system adapted to recycle instruction handling control sequences in response to occurrence of error an improved sequence control section comprising: re-execution control means settable to a plurality of states useful to condition sub-sequence branch selection in control sequences; and re-entrant sequence control means conditioned by said re-execution control means at a first predetermined stage of said sequence to select between alternate long and short branch sub-sequences of said control sequence which terminate coincidentally at a second predetermined subsequent stage of said sequence; said re-execution control means being settable to different said states by operations of said sequence control means occurrent only in said long sub-sequence and in a sub-sequent final stage of said sequence and not in said short sub-sequence.
Claim 5
Dependent Claim
124 words
In a data processing system adapted to recycle instruction handling control sequences in response to occurrence of error an improved sequence control section comprising: re-execution control means settable to a plurality of states useful to condition sub-sequence branch selection in control sequences; and re-entrant sequence control means conditioned by said re-execution control means at a first predetermined stage of said sequence to select between alternate long and short branch sub-sequences of said control sequence which terminate coincidentally at a second predetermined subsequent stage of said sequence; said re-execution control means being settable to different said states by operations of said sequence control means occurrent only in said long sub-sequence and in a sub-sequent final stage of said sequence and not in said short sub-sequence.
Claim 6
Dependent Claim
97 words
A data processing control section according to claim 3 wherein; said re-execution control means is a binary storage element conditionable to distinct set and reset states; said sequence control means is operative to select between said long and short branch sub-sequences at said first predetermined stage in dependence respectively upon existence of said reset and set states in said re-execution control means; and said sequence control means is operative to condition said re-execution control means respectively to said set state during said long branch sub-sequence and to said reset state in said final stage of said sequence.
Claim 7
Dependent Claim
62 words
A control section according to claim 4 in which: said long branch sub-sequence encompasses control of successive operations to manipulate source data and to store and verify result data produced by said manipulation; said verification preceding conditioning of said re-execution control means to said set state; and said short branch encompasses only operations incidental to recovery and utilization of said result data.
Claim 8
Dependent Claim
57 words
A control section according to claim 5 wherein: said result data is stored in regular process storage and back-up saving storage; said control sequence subsequent to said second predetermined stage encompasses operations resulting in overwriting of said regular process storage; and said short sub-sequence encompasses transferral of said result data between said saving storage and regular storage.
Claim 9
Dependent Claim
138 words
In a data processing system improved sequence control apparatus comprising: sequence control means operative to control original cycling and error dependent recycling of a predetermined plural step sequence of operations, said sequence comprising discrete entry and exit stages and an intermediate sub-sequence of variable length commencing and terminating at respective first and second predetermined intermediate stages of said sequence; said sub-sequence comprising alternately selectable long and short branch sub-sequences; bistable re-execution control means conditionable to distinct reset and set states for controlling respective selection of said long and short branch sub-sequences by said sequence control means; said reset state being conditioned by operations of said sequence control means prior to said entry stage and at said exit stage; and said set state being conditioned by said sequence control means at a predetermined stage in said lOng branch sub-sequence.
Claim 10
Dependent Claim
138 words
In a data processing system improved sequence control apparatus comprising: sequence control means operative to control original cycling and error dependent recycling of a predetermined plural step sequence of operations, said sequence comprising discrete entry and exit stages and an intermediate sub-sequence of variable length commencing and terminating at respective first and second predetermined intermediate stages of said sequence; said sub-sequence comprising alternately selectable long and short branch sub-sequences; bistable re-execution control means conditionable to distinct reset and set states for controlling respective selection of said long and short branch sub-sequences by said sequence control means; said reset state being conditioned by operations of said sequence control means prior to said entry stage and at said exit stage; and said set state being conditioned by said sequence control means at a predetermined stage in said lOng branch sub-sequence.
Claim 11
Dependent Claim
91 words
In sequence control apparatus according to claim 16: additional bistable re-execution control means receiving respective set conditioning from said sequence control means at predetermined stages of respective additional long branch sub-sequences occurrent intermediate said second intermediate stage and exit stage of said sequence and receiving joint reset conditioning from said sequence control means at said exit stage of said sequence; said additional control means controlling selection of said respective additional long branch sub-sequences when in reset condition and controlling alternate selection of respective short branch sub-sequences when in said set condition.
Claim 12
Dependent Claim
61 words
Apparatus according to claim 8 wherein said additional control means are general purpose condition triggers having general control functions; wherein the then existing states of said triggers are preserved in back-up storage by operation of said sequence control means prior to first execution of said additional long sub-sequences and restored to said triggers prior to said exit stage of said sequence.
Claim 13
Dependent Claim
132 words
In a data processing system containing a fast-access scratchpad store, sequence control section and plural condition triggers associated with sequence branching functions of the control section, the improvement comprising: the adaptation of said control section to include re-entrant recycling of a plurality of discrete control sequences each containing discrete entry and exit stages and an intermediate stage consisting of alternatively selectable long and short branch sub-sequences which are selectable according to the reset/set state of a predetermined one of said condition triggers; said long sub-sequence including in succession manipulation of source data, verification of result data produced by said manipulation, said result data and set conditioning of said predetermined one trigger; said short sub-sequence consisting of retrieval of said saved result data; said one trigger receiving reset conditioning at said exit stage.
Claim 14
Dependent Claim
132 words
In a data processing system containing a fast-access scratchpad store, sequence control section and plural condition triggers associated with sequence branching functions of the control section, the improvement comprising: the adaptation of said control section to include re-entrant recycling of a plurality of discrete control sequences each containing discrete entry and exit stages and an intermediate stage consisting of alternatively selectable long and short branch sub-sequences which are selectable according to the reset/set state of a predetermined one of said condition triggers; said long sub-sequence including in succession manipulation of source data, verification of result data produced by said manipulation, said result data and set conditioning of said predetermined one trigger; said short sub-sequence consisting of retrieval of said saved result data; said one trigger receiving reset conditioning at said exit stage.
Claim 15
Dependent Claim
28 words
Processing system controls according to claim 10 wherein said result saving operation comprises transferral of said verified result data to a predetermined saving location in said scratchpad store.
Claim 16
Dependent Claim
57 words
Processing controls according to claim 11 wherein said scratchpad store comprises a plurality of input registers arranged as a queueing pipe-line for receiving and delaying storage of said result data until a corresponding result data representation is verified elsewhere; whereby the ultimate scratchpad location of said result data is not altered prior to completion of said verification.
Claim 17
Dependent Claim
228 words
In a data processing system, containing program storage, fast-access temporary storage and sequence controls and which is adapted to execute certain variable field length program instructions by extracting a variable length operand piecemeal from a series of program storage addresses designated by a repeatedly modified basic relative address quantity, by processing said operand piecemeal to produce a variable field length result and by ultimately storing said result piecemeal in program storage locations occupied by said operand, the improvement comprising: means adapting said controls to first temporarily store said basic address quantity and said piecemeal result in said temporary storage until all pieces thereof have been produced and only thereafter to transfer said result piecemeal from said temporary storage of said program storage; means for monitoring said system for error during the formation, temporary storage and final program storage of said result and for initiating recycling of said controls upon error; binary state sequence conditioning means reset prior to each instruction control sequence and set by said adapted controls and monitoring means upon error-free completion of temporary storage of said results and prior to transfer of said result to a program storage; said controls being conditIoned selectively during said recycling to skip over said piecemeal operand process and to proceed directly with said temporary storage to program storage result transfer wherein said sequence conditioning means is in set condition.
Claim 18
Dependent Claim
228 words
In a data processing system, containing program storage, fast-access temporary storage and sequence controls and which is adapted to execute certain variable field length program instructions by extracting a variable length operand piecemeal from a series of program storage addresses designated by a repeatedly modified basic relative address quantity, by processing said operand piecemeal to produce a variable field length result and by ultimately storing said result piecemeal in program storage locations occupied by said operand, the improvement comprising: means adapting said controls to first temporarily store said basic address quantity and said piecemeal result in said temporary storage until all pieces thereof have been produced and only thereafter to transfer said result piecemeal from said temporary storage of said program storage; means for monitoring said system for error during the formation, temporary storage and final program storage of said result and for initiating recycling of said controls upon error; binary state sequence conditioning means reset prior to each instruction control sequence and set by said adapted controls and monitoring means upon error-free completion of temporary storage of said results and prior to transfer of said result to a program storage; said controls being conditIoned selectively during said recycling to skip over said piecemeal operand process and to proceed directly with said temporary storage to program storage result transfer wherein said sequence conditioning means is in set condition.
Claim 19
Dependent Claim
112 words
In a data processing system: a plurality of binary elements representing sequence branch conditioning triggers; and a sequence control unit adapted in connection with execution of a particular multi-stage sequence to establish all of said elements initially in a reset condition and subsequently during progressive stages of execution of said particular sequence to establish individual said elements in set conditions; means for monitoring said system for error and for causing said control unit to recycle upon occurrence of error; said control unit adapted during recycling of said particular sequence to alternately skip or cycle multi-stage skip portions of said sequence when respective said binary elements are respectively in set or reset condition.
Claim 20
Dependent Claim
112 words
In a data processing system: a plurality of binary elements representing sequence branch conditioning triggers; and a sequence control unit adapted in connection with execution of a particular multi-stage sequence to establish all of said elements initially in a reset condition and subsequently during progressive stages of execution of said particular sequence to establish individual said elements in set conditions; means for monitoring said system for error and for causing said control unit to recycle upon occurrence of error; said control unit adapted during recycling of said particular sequence to alternately skip or cycle multi-stage skip portions of said sequence when respective said binary elements are respectively in set or reset condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-04 | 1975-10-04 | 1976-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-04 | 1979-10-04 | 1980-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-04 | 1983-10-04 | 1984-04-04 | $7700.00 | Window Closed / Lapsed |